s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE

jordens · sbourdeauducq · commit d6c19858faf0 · 2015-04-10T16:12:29.000+08:00
diff --git a/misoclib/mem/sdram/phy/s6ddrphy.py b/misoclib/mem/sdram/phy/s6ddrphy.py
@@ -69,15 +69,18 @@ def __init__(self, pads, module, rd_bitslip, wr_bitslip, dqs_ddr_alignment):
 		#             sys_clk   ----____----____
 		#  phase_sel(nphases=2) 0   1   0   1     Half Rate
 		phase_sel = Signal(log2_int(nphases))
-		sys_clk_d = Signal()
+		phase_half = Signal.like(phase_sel)
+		phase_sys = Signal.like(phase_half)
+
+		sd_sys += phase_sys.eq(phase_half)
 
 		sd_sdram_half += [
-			If(sys_clk & ~sys_clk_d,
-				phase_sel.eq(0)
+			If(phase_half == phase_sys,
+				phase_sel.eq(0),
 			).Else(
 				phase_sel.eq(phase_sel+1)
 			),
-			sys_clk_d.eq(sys_clk)
+			phase_half.eq(phase_half+1),
 		]
 
 		# register dfi cmds on half_rate clk
diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
@@ -61,8 +61,6 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa
 		platform.add_platform_command("""
 INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
-
-PIN "mxcrg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
 """)
 		platform.add_source_dir(os.path.join("misoclib", "others", "mxcrg"))
 
diff --git a/targets/pipistrello.py b/targets/pipistrello.py
@@ -110,9 +110,6 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa
 				self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
 				self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
 			]
-			platform.add_platform_command("""
-	PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
-	""")
 			self.register_sdram_phy(self.ddrphy)
 
 		if not self.integrated_rom_size:

Original file line number	Diff line number	Diff line change
`@@ -110,9 +110,6 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa`
`110`	`110`	`self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),`
`111`	`111`	`self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),`
`112`	`112`	`]`
`113`		`- platform.add_platform_command("""`
`114`		`- PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;`
`115`		`- """)`
`116`	`113`	`self.register_sdram_phy(self.ddrphy)`
`117`	`114`
`118`	`115`	`if not self.integrated_rom_size:`