Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 3a2b677f85ca
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: ea613cd8eef4
Choose a head ref
  • 2 commits
  • 5 files changed
  • 1 contributor

Commits on Apr 8, 2015

  1. Copy the full SHA
    03aa972 View commit details
  2. Copy the full SHA
    ea613cd View commit details
8 changes: 4 additions & 4 deletions misoclib/com/liteeth/generic/__init__.py
Original file line number Diff line number Diff line change
@@ -29,15 +29,15 @@ def transform_instance(self, submodule):
# add buffer on sinks
for name, sink in sinks.items():
buf = Buffer(sink.description)
self.submodules += buf
submodule.submodules += buf
setattr(self, name, buf.d)
self.comb += Record.connect(buf.q, sink)
submodule.comb += Record.connect(buf.q, sink)

# add buffer on sources
for name, source in sources.items():
buf = Buffer(source.description)
self.submodules += buf
self.comb += Record.connect(source, buf.d)
submodule.submodules += buf
submodule.comb += Record.connect(source, buf.d)
setattr(self, name, buf.q)

class EndpointPacketStatus(Module):
8 changes: 4 additions & 4 deletions misoclib/mem/litesata/common.py
Original file line number Diff line number Diff line change
@@ -270,15 +270,15 @@ def transform_instance(self, submodule):
# add buffer on sinks
for name, sink in sinks.items():
buf = Buffer(sink.description)
self.submodules += buf
submodule.submodules += buf
setattr(self, name, buf.d)
self.comb += Record.connect(buf.q, sink)
submodule.comb += Record.connect(buf.q, sink)

# add buffer on sources
for name, source in sources.items():
buf = Buffer(source.description)
self.submodules += buf
self.comb += Record.connect(source, buf.d)
submodule.submodules += buf
submodule.comb += Record.connect(source, buf.d)
setattr(self, name, buf.q)

class EndpointPacketStatus(Module):
4 changes: 2 additions & 2 deletions misoclib/mem/litesata/core/link/__init__.py
Original file line number Diff line number Diff line change
@@ -35,7 +35,7 @@ def __init__(self, phy):

# inserter CONT and scrambled data between
# CONT and next primitive
cont = BufferizeEndpoints(LiteSATACONTInserter(phy_description(32)), "source")
cont = BufferizeEndpoints("source")(LiteSATACONTInserter(phy_description(32)))
self.submodules += cont

# datas / primitives mux
@@ -121,7 +121,7 @@ def __init__(self, phy):
self.submodules += fsm

# CONT remover
cont = BufferizeEndpoints(LiteSATACONTRemover(phy_description(32)), "source")
cont = BufferizeEndpoints("source")(LiteSATACONTRemover(phy_description(32)))
self.submodules += cont
self.comb += Record.connect(phy.source, cont.sink)

11 changes: 7 additions & 4 deletions misoclib/mem/litesata/example_designs/make.py
Original file line number Diff line number Diff line change
@@ -69,8 +69,11 @@ def _get_args():
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
try:
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
except:
pass

# decode actions
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
@@ -139,8 +142,8 @@ def _get_args():
MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
}
src = verilog.convert(soc, ios, special_overrides=so)
tools.write_to_file("build/litesata.v", src)
v_output = verilog.convert(soc, ios, special_overrides=so)
v_output.write("build/litesata.v")

if actions["build-bitstream"]:
vns = platform.build(soc, build_name=build_name, run=True)
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from mibuild.generic_platform import *
from mibuild.xilinx.common import CRG_DS
from mibuild.xilinx.vivado import XilinxVivadoPlatform
from mibuild.xilinx.platform import XilinxPlatform

_io = [
("sys_clk", 0, Pins("X")),
@@ -16,9 +15,9 @@
),
]

class Platform(XilinxVivadoPlatform):
def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk200", "cpu_reset"), **kwargs):
XilinxVivadoPlatform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
class Platform(XilinxPlatform):
def __init__(self, device="xc7k325t", programmer=""):
XilinxPlatform.__init__(self, device, _io)

def do_finalize(self, *args, **kwargs):
pass