File tree 1 file changed +19
-3
lines changed
misoclib/cpu/peripherals/timer
1 file changed +19
-3
lines changed Original file line number Diff line number Diff line change 1
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from migen .fhdl .std import *
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from migen .bank .description import *
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from migen .bank .eventmanager import *
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+ from migen .genlib .misc import Counter
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class Timer (Module , AutoCSR ):
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- def __init__ (self , width = 32 ):
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+ def __init__ (self , width = 32 , prescaler_width = 32 ):
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self ._load = CSRStorage (width )
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self ._reload = CSRStorage (width )
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self ._en = CSRStorage ()
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+ self ._prescaler = CSRStorage (prescaler_width , reset = 1 )
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self ._update_value = CSR ()
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self ._value = CSRStatus (width )
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@@ -15,14 +17,28 @@ def __init__(self, width=32):
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self .ev .finalize ()
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###
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+ enable = self ._en .storage
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+ tick = Signal ()
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+
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+ counter = Counter (prescaler_width )
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+ self .submodules += counter
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+ self .comb += [
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+ If (enable ,
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+ tick .eq (counter .value >= (self ._prescaler .storage - 1 )),
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+ counter .ce .eq (1 ),
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+ counter .reset .eq (tick ),
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+ ).Else (
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+ counter .reset .eq (1 )
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+ )
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+ ]
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value = Signal (width )
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self .sync += [
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- If (self . _en . storage ,
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+ If (enable ,
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If (value == 0 ,
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# set reload to 0 to disable reloading
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value .eq (self ._reload .storage )
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- ).Else (
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+ ).Elif ( tick ,
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value .eq (value - 1 )
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)
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).Else (
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