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timer: add prescaler
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enjoy-digital committed Apr 10, 2015
1 parent d6c1985 commit 80ef729
Showing 1 changed file with 19 additions and 3 deletions.
22 changes: 19 additions & 3 deletions misoclib/cpu/peripherals/timer/__init__.py
Original file line number Diff line number Diff line change
@@ -1,12 +1,14 @@
from migen.fhdl.std import *
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.genlib.misc import Counter

class Timer(Module, AutoCSR):
def __init__(self, width=32):
def __init__(self, width=32, prescaler_width=32):
self._load = CSRStorage(width)
self._reload = CSRStorage(width)
self._en = CSRStorage()
self._prescaler = CSRStorage(prescaler_width, reset=1)
self._update_value = CSR()
self._value = CSRStatus(width)

@@ -15,14 +17,28 @@ def __init__(self, width=32):
self.ev.finalize()

###
enable = self._en.storage
tick = Signal()

counter = Counter(prescaler_width)
self.submodules += counter
self.comb += [
If(enable,
tick.eq(counter.value >= (self._prescaler.storage-1)),

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@sbourdeauducq

sbourdeauducq Apr 10, 2015

Member

Wouldn't == be more efficient?

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@sbourdeauducq

sbourdeauducq Apr 10, 2015

Member

Hmm, then you'd have to handle the case prescaler=1 separately...

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@sbourdeauducq

sbourdeauducq Apr 10, 2015

Member

What about counting down? (like the timer)

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@sbourdeauducq

sbourdeauducq Apr 10, 2015

Member

And why is a prescaler better than a wider timestamp counter?

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@enjoy-digital

enjoy-digital Apr 10, 2015

Author Contributor

Thanks for the suggestions, I've implemented the prescaler in software as you suggested, it's working so I reverted the prescaler core in the Timer.

counter.ce.eq(1),
counter.reset.eq(tick),
).Else(
counter.reset.eq(1)
)
]

value = Signal(width)
self.sync += [
If(self._en.storage,
If(enable,
If(value == 0,
# set reload to 0 to disable reloading
value.eq(self._reload.storage)
).Else(
).Elif(tick,
value.eq(value - 1)
)
).Else(

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