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Commit 44304a3

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committedApr 8, 2015
soc,runtime: define RTIO FUD channel number in targets
1 parent efd1c24 commit 44304a3

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4 files changed

+6
-4
lines changed

4 files changed

+6
-4
lines changed
 

Diff for: ‎soc/runtime/rtio.c

-2
Original file line numberDiff line numberDiff line change
@@ -91,8 +91,6 @@ int rtio_pileup_count(int channel)
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return r;
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}
9393

94-
#define RTIO_FUD_CHANNEL 8
95-
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void rtio_fud_sync(void)
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{
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while(rtio_get_counter() < previous_fud_end_time);

Diff for: ‎soc/targets/artiq_kc705.py

+1
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
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rtio_ins = [platform.request("pmt") for i in range(2)]
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rtio_outs = [platform.request("ttl", i) for i in range(16)]
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rtio_outs.append(platform.request("user_led", 2))
55+
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
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rtio_outs.append(fud)
5657

5758
self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)

Diff for: ‎soc/targets/artiq_pipistrello.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -69,9 +69,10 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
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rtio_ins = [platform.request("pmt", i) for i in range(2)]
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rtio_ins += [platform.request("xtrig", 0)]
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rtio_outs = [platform.request("ttl", i) for i in range(16)]
72-
rtio_outs += [fud]
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rtio_outs += [platform.request("ext_led", 0)]
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rtio_outs += [platform.request("user_led", i) for i in range(2, 5)]
74+
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
75+
rtio_outs.append(fud)
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self.submodules.rtiocrg = _RTIOCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(

Diff for: ‎soc/targets/artiq_ppro.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,9 @@ def __init__(self, platform, cpu_type="or1k",
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platform.request("ttl_h_tx_en").eq(1)
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]
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rtio_ins = [platform.request("pmt") for i in range(2)]
81-
rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud]
81+
rtio_outs = [platform.request("ttl", i) for i in range(5)]
82+
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
83+
rtio_outs.append(fud)
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8385
self.submodules.rtiocrg = _RTIOMiniCRG(platform)
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self.submodules.rtiophy = rtio.phy.SimplePHY(

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