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soc,runtime: define RTIO FUD channel number in targets
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sbourdeauducq committed Apr 8, 2015

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1 parent efd1c24 commit 44304a3
Showing 4 changed files with 6 additions and 4 deletions.
2 changes: 0 additions & 2 deletions soc/runtime/rtio.c
Original file line number Diff line number Diff line change
@@ -91,8 +91,6 @@ int rtio_pileup_count(int channel)
return r;
}

#define RTIO_FUD_CHANNEL 8

void rtio_fud_sync(void)
{
while(rtio_get_counter() < previous_fud_end_time);
1 change: 1 addition & 0 deletions soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -52,6 +52,7 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(16)]
rtio_outs.append(platform.request("user_led", 2))
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
rtio_outs.append(fud)

self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
3 changes: 2 additions & 1 deletion soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -69,9 +69,10 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
rtio_ins = [platform.request("pmt", i) for i in range(2)]
rtio_ins += [platform.request("xtrig", 0)]
rtio_outs = [platform.request("ttl", i) for i in range(16)]
rtio_outs += [fud]
rtio_outs += [platform.request("ext_led", 0)]
rtio_outs += [platform.request("user_led", i) for i in range(2, 5)]
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
rtio_outs.append(fud)

self.submodules.rtiocrg = _RTIOCRG(platform)
self.submodules.rtiophy = rtio.phy.SimplePHY(
4 changes: 3 additions & 1 deletion soc/targets/artiq_ppro.py
Original file line number Diff line number Diff line change
@@ -78,7 +78,9 @@ def __init__(self, platform, cpu_type="or1k",
platform.request("ttl_h_tx_en").eq(1)
]
rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(5)] + [fud]
rtio_outs = [platform.request("ttl", i) for i in range(5)]
self.add_constant("RTIO_FUD_CHANNEL", len(rtio_ins) + len(rtio_outs))
rtio_outs.append(fud)

self.submodules.rtiocrg = _RTIOMiniCRG(platform)
self.submodules.rtiophy = rtio.phy.SimplePHY(

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