10
10
class SyncFIFOCase (SimCase , unittest .TestCase ):
11
11
class TestBench (Module ):
12
12
def __init__ (self ):
13
- self .submodules .dut = SyncFIFO ([( "a" , 32 ), ( "b" , 32 )] , 2 )
13
+ self .submodules .dut = SyncFIFO (64 , 2 )
14
14
15
15
self .sync += [
16
16
If (self .dut .we & self .dut .writable ,
17
- self .dut .din . a . eq (self .dut .din . a + 1 ),
18
- self .dut .din . b . eq (self .dut .din . b + 2 )
17
+ self .dut .din [: 32 ]. eq (self .dut .din [: 32 ] + 1 ),
18
+ self .dut .din [ 32 :]. eq (self .dut .din [ 32 :] + 2 )
19
19
)
20
20
]
21
21
22
- def test_sizes (self ):
23
- self .assertEqual (len (self .tb .dut .din_bits ), 64 )
24
- self .assertEqual (len (self .tb .dut .dout_bits ), 64 )
25
-
26
22
def test_run_sequence (self ):
27
23
seq = list (range (20 ))
28
24
def gen ():
@@ -36,8 +32,8 @@ def gen():
36
32
i = seq .pop (0 )
37
33
except IndexError :
38
34
break
39
- self .assertEqual ((yield self .tb .dut .dout . a ), i )
40
- self .assertEqual ((yield self .tb .dut .dout . b ), i * 2 )
35
+ self .assertEqual ((yield self .tb .dut .dout [: 32 ] ), i )
36
+ self .assertEqual ((yield self .tb .dut .dout [ 32 :] ), i * 2 )
41
37
yield
42
38
self .run_with (gen ())
43
39
@@ -48,13 +44,13 @@ def gen():
48
44
yield self .tb .dut .we .eq (cycle % 2 == 0 )
49
45
yield self .tb .dut .re .eq (cycle % 7 == 0 )
50
46
yield self .tb .dut .replace .eq (
51
- (yield self .tb .dut .din . a ) % 5 == 1 )
47
+ (yield self .tb .dut .din [: 32 ] ) % 5 == 1 )
52
48
if (yield self .tb .dut .readable ) and (yield self .tb .dut .re ):
53
49
try :
54
50
i = seq .pop (0 )
55
51
except IndexError :
56
52
break
57
- self .assertEqual ((yield self .tb .dut .dout . a ), i )
58
- self .assertEqual ((yield self .tb .dut .dout . b ), i * 2 )
53
+ self .assertEqual ((yield self .tb .dut .dout [: 32 ] ), i )
54
+ self .assertEqual ((yield self .tb .dut .dout [ 32 :] ), i * 2 )
59
55
yield
60
56
self .run_with (gen ())
0 commit comments