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sim: make sure replaced memory signals are always in VCD signal set
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sbourdeauducq committed Oct 5, 2015
1 parent 70e3280 commit e0899c1
Showing 1 changed file with 2 additions and 0 deletions.
2 changes: 2 additions & 0 deletions migen/sim/core.py
Original file line number Diff line number Diff line change
@@ -237,6 +237,8 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 10}, vcd_name=
signals.add(cd.clk)
if cd.rst is not None:
signals.add(cd.rst)
for memory_array in mta.replacements.values():
signals |= set(memory_array)
signals = sorted(signals, key=lambda x: x.duid)
self.vcd = VCDWriter(vcd_name, signals)

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