targets/atlys_edid_debug: update LiteScope

enjoy-digital · enjoy-digital · commit 9e9da3b7b71a · 2015-09-27T19:48:46.000+02:00
diff --git a/targets/atlys_edid_debug.py b/targets/atlys_edid_debug.py
@@ -6,7 +6,7 @@
 
 from litescope.common import *
 from litescope.core.port import LiteScopeTerm
-from litescope.frontend.la import LiteScopeLA
+from litescope.frontend.logic_analyzer import LiteScopeLogicAnalyzer
 
 class UARTVirtualPhy:
     def __init__(self):
@@ -16,7 +16,7 @@ def __init__(self):
 
 class EDIDDebugSoC(VideomixerSoC):
     csr_map = {
-        "la": 30
+        "logic_analyzer": 30
     }
     csr_map.update(VideomixerSoC.csr_map)
 
@@ -61,8 +61,8 @@ def __init__(self, platform, with_uart=False, **kwargs):
             self.hdmi_in0.edid.din,
             self.hdmi_in0_edid_fsm_state
         )
-        self.submodules.la = LiteScopeLA(self.debug, 32*1024, with_subsampler=True)
-        self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
+        self.submodules.logic_analyzer = LiteScopeLogicAnalyzer(self.debug, 32*1024, with_subsampler=True)
+        self.logic_analyzer.trigger.add_port(LiteScopeTerm(self.logic_analyzer.dw))
 
     def do_finalize(self):
         VideomixerSoC.do_finalize(self)
@@ -71,6 +71,6 @@ def do_finalize(self):
         ]
 
     def do_exit(self, vns):
-        self.la.export(vns, "../../test/edid_debug/la.csv") # XXX
+        self.logic_analyzer.export(vns, "../../test/edid_debug/logic_analyzer.csv") # XXX
 
 default_subtarget = EDIDDebugSoC
diff --git a/test/edid_debug/test_la.py b/test/edid_debug/test_la.py
@@ -1,23 +1,23 @@
-from litescope.software.driver.la import LiteScopeLADriver
+from litescope.software.driver.logic_analyzer import LiteScopeLogicAnalyzerDriver
 
 
 def main(wb):
     wb.open()
     # # #
-    la = LiteScopeLADriver(wb.regs, "la", debug=True)
+    logic_analyzer = LiteScopeLogicAnalyzerDriver(wb.regs, "logic_analyzer", debug=True)
 
 #    cond = {"hdmi_in0_edid_scl_raw" : 0}
     cond = {"hdmi_in0_edid_fsm_state" : 2}
 #    cond = {}
-    la.configure_term(port=0, cond=cond)
-    la.configure_sum("term")
-    la.configure_subsampler(64)
-    la.run(offset=128, length=8192)
+    logic_analyzer.configure_term(port=0, cond=cond)
+    logic_analyzer.configure_sum("term")
+    logic_analyzer.configure_subsampler(64)
+    logic_analyzer.run(offset=128, length=8192)
 
-    while not la.done():
+    while not logic_analyzer.done():
         pass
-    la.upload()
+    logic_analyzer.upload()
 
-    la.save("dump.vcd")
+    logic_analyzer.save("dump.vcd")
     # # #
     wb.close()
