m-labs · Sep 28, 2015 · Sep 28, 2015
diff --git a/.gitignore b/.gitignore
@@ -1,15 +1,3 @@
 __pycache__
-build/*
-*.o
-*.d
-*.a
-*.elf
-*.bin
-*.fbi
-tools/flterm
-tools/byteswap
-software/include/generated/*.h
-software/include/generated/*.ld
-software/include/generated/*.mak
 *.vcd
 outgoing
diff --git a/.gitmodules b/.gitmodules
@@ -4,9 +4,9 @@
 [submodule "misoc/cores/mor1kx/verilog"]
 	path = misoc/cores/mor1kx/verilog
 	url = https://github.com/openrisc/mor1kx.git
-[submodule "software/compiler-rt"]
-	path = software/compiler-rt
+[submodule "misoc/software/compiler_rt"]
+	path = misoc/software/compiler_rt
 	url = http://llvm.org/git/compiler-rt.git
-[submodule "software/unwinder"]
-	path = software/unwinder
+[submodule "misoc/software/unwinder"]
+	path = misoc/software/unwinder
 	url = https://github.com/whitequark/libunwind
diff --git a/crc.py b/crc.py
diff --git a/flash_extra.py b/flash_extra.py
diff --git a/make.py b/make.py
diff --git a/misoc/cores/identifier.py b/misoc/cores/identifier.py
@@ -1,28 +1,16 @@
-import subprocess
-
 from migen import *
 
 from misoc.interconnect.csr import *
 
 
-def get_id():
-    output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
-    return int(output[:8], 16)
-
-
 class Identifier(Module, AutoCSR):
     def __init__(self, sysid, frequency, revision=None):
         self._sysid = CSRStatus(16)
-        self._revision = CSRStatus(32)
         self._frequency = CSRStatus(32)
 
         ###
 
-        if revision is None:
-            revision = get_id()
-
         self.comb += [
             self._sysid.status.eq(sysid),
-            self._revision.status.eq(revision),
             self._frequency.status.eq(frequency)
         ]