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  • 3 commits
  • 5 files changed
  • 2 contributors

Commits on Jul 17, 2013

  1. s6ddrphy: revert CAS LATENCY 3 (configurable CAS Latency was buggy)

    enjoy-digital authored and Sebastien Bourdeauducq committed Jul 17, 2013
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    fb06d80 View commit details
  2. cif: fix indentation

    Sebastien Bourdeauducq committed Jul 17, 2013
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    da2b7aa View commit details
  3. s6ddrphy: cleanup

    Sebastien Bourdeauducq committed Jul 17, 2013
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    ea65aaa View commit details
Showing with 164 additions and 161 deletions.
  1. +115 −115 milkymist/cif.py
  2. +3 −4 milkymist/lasmicon/__init__.py
  3. +1 −1 milkymist/lasmicon/multiplexer.py
  4. +34 −20 milkymist/s6ddrphy/__init__.py
  5. +11 −21 top.py
230 changes: 115 additions & 115 deletions milkymist/cif.py
Original file line number Diff line number Diff line change
@@ -67,30 +67,30 @@ def get_csr_header(csr_base, bank_array, interrupt_map):
return r

def get_sdram_phy_header(sdram_phy):
if sdram_phy.phy_settings.type not in ["SDR", "DDR", "LPDDR", "DDR2"]:
raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")
if sdram_phy.phy_settings.memtype not in ["SDR", "DDR", "LPDDR", "DDR2"]:
raise NotImplementedError("The SDRAM PHY header generator only supports SDR, DDR, LPDDR and DDR2")

r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"
r = "#ifndef __HW_SDRAM_PHY_H\n#define __HW_SDRAM_PHY_H\n"
r += "#include <hw/common.h>\n#include <hw/csr.h>\n#include <hw/flags.h>\n\n"

r += "static void cdelay(int i);\n"
r += "static void cdelay(int i);\n"

#
# commands_px functions
#
for n in range(sdram_phy.phy_settings.nphases):
r += """
#
# commands_px functions
#
for n in range(sdram_phy.phy_settings.nphases):
r += """
static void command_p{n}(int cmd)
{{
dfii_pi{n}_command_write(cmd);
dfii_pi{n}_command_issue_write(1);
}}""".format(n=str(n))
r += "\n\n"
r += "\n\n"

#
# rd/wr access macros
#
r += """
#
# rd/wr access macros
#
r += """
#define dfii_pird_address_write(X) dfii_pi{rdphase}_address_write(X)
#define dfii_piwr_address_write(X) dfii_pi{wrphase}_address_write(X)
@@ -100,105 +100,105 @@ def get_sdram_phy_header(sdram_phy):
#define command_prd(X) command_p{rdphase}(X)
#define command_pwr(X) command_p{wrphase}(X)
""".format(rdphase=str(sdram_phy.phy_settings.rdphase), wrphase=str(sdram_phy.phy_settings.wrphase))
r +="\n"

#
# init sequence
#
cmds = {
"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
"AUTO_REFRESH" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
"CKE" : "DFII_CONTROL_CKE"
}

def gen_cmd(comment, a, ba, cmd, delay):
r = "\t/* {0} */\n".format(comment)
r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
if "CKE" in cmd:
r += "\tdfii_control_write({0});\n".format(cmd)
else:
r += "\tcommand_p0({0});\n".format(cmd)
r += "\tcdelay({0:d});\n".format(delay)
r += "\n"
return r


r += "static void init_sequence(void)\n{\n"

cl = sdram_phy.phy_settings.cl

if sdram_phy.phy_settings.type == "SDR":
bl = 1*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

elif sdram_phy.phy_settings.type == "DDR":
bl = 2*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
emr = 0
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

elif sdram_phy.phy_settings.type == "LPDDR":
bl = 2*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
emr = 0
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

elif sdram_phy.phy_settings.type == "DDR2":
bl = 2*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
emr = 0
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

for comment, a, ba, cmd, delay in init_sequence:
r += gen_cmd(comment, a, ba, cmd, delay)
r +="\n"

#
# init sequence
#
cmds = {
"PRECHARGE_ALL" : "DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
"MODE_REGISTER" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_WE|DFII_COMMAND_CS",
"AUTO_REFRESH" : "DFII_COMMAND_RAS|DFII_COMMAND_CAS|DFII_COMMAND_CS",
"CKE" : "DFII_CONTROL_CKE"
}

def gen_cmd(comment, a, ba, cmd, delay):
r = "\t/* {0} */\n".format(comment)
r += "\tdfii_pi0_address_write({0:#x});\n".format(a)
r += "\tdfii_pi0_baddress_write({0:d});\n".format(ba)
if "CKE" in cmd:
r += "\tdfii_control_write({0});\n".format(cmd)
else:
r += "\tcommand_p0({0});\n".format(cmd)
r += "\tcdelay({0:d});\n".format(delay)
r += "\n"
return r

r += "}\n"
r += "#endif\n"

return r
r += "static void init_sequence(void)\n{\n"

cl = sdram_phy.phy_settings.cl

if sdram_phy.phy_settings.memtype == "SDR":
bl = 1*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

elif sdram_phy.phy_settings.memtype == "DDR":
bl = 2*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
emr = 0
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

elif sdram_phy.phy_settings.memtype == "LPDDR":
bl = 2*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
emr = 0
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Extended Mode Register", emr, 2, cmds["MODE_REGISTER"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

elif sdram_phy.phy_settings.memtype == "DDR2":
bl = 2*sdram_phy.phy_settings.nphases
mr = log2_int(bl) + (cl << 4)
emr = 0
reset_dll = 1 << 8

init_sequence = [
("Bring CKE high", 0x0000, 0, cmds["CKE"], 2000),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Load Extended Mode Register", emr, 1, cmds["MODE_REGISTER"], 0),
("Load Mode Register / Reset DLL, CL={0:d}, BL={1:d}".format(cl, bl), mr + reset_dll, 0, cmds["MODE_REGISTER"], 200),
("Precharge All", 0x0400, 0, cmds["PRECHARGE_ALL"], 0),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Auto Refresh", 0x0, 0, cmds["AUTO_REFRESH"], 4),
("Load Mode Register / CL={0:d}, BL={1:d}".format(cl, bl), mr, 0, cmds["MODE_REGISTER"], 200)
]

for comment, a, ba, cmd, delay in init_sequence:
r += gen_cmd(comment, a, ba, cmd, delay)

r += "}\n"
r += "#endif\n"

return r
7 changes: 3 additions & 4 deletions milkymist/lasmicon/__init__.py
Original file line number Diff line number Diff line change
@@ -7,14 +7,13 @@
from milkymist.lasmicon.bankmachine import *
from milkymist.lasmicon.multiplexer import *

PhySettings = namedtuple("PhySettings", "type dfi_d nphases rdphase wrphase cl")
PhySettings = namedtuple("PhySettings", "memtype dfi_d nphases rdphase wrphase cl read_latency write_latency")

class GeomSettings(namedtuple("_GeomSettings", "bank_a row_a col_a")):
def __init__(self, *args, **kwargs):
self.mux_a = max(self.row_a, self.col_a)

TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \
" read_latency write_latency" \
" req_queue_size read_time write_time")

class LASMIcon(Module):
@@ -31,8 +30,8 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
dw=phy_settings.dfi_d*phy_settings.nphases,
nbanks=2**geom_settings.bank_a,
req_queue_size=timing_settings.req_queue_size,
read_latency=timing_settings.read_latency+1,
write_latency=timing_settings.write_latency+1)
read_latency=phy_settings.read_latency+1,
write_latency=phy_settings.write_latency+1)
self.nrowbits = geom_settings.col_a - address_align

###
2 changes: 1 addition & 1 deletion milkymist/lasmicon/multiplexer.py
Original file line number Diff line number Diff line change
@@ -178,7 +178,7 @@ def anti_starvation(timeout):
steerer.sel[0].eq(STEER_REFRESH),
If(~refresher.req, NextState("READ"))
)
fsm.delayed_enter("RTW", "WRITE", timing_settings.read_latency-1)
fsm.delayed_enter("RTW", "WRITE", phy_settings.read_latency-1) # FIXME: reduce this, actual limit is around (cl+1)/nphases
fsm.delayed_enter("WTR", "READ", timing_settings.tWTR-1)
# FIXME: workaround for zero-delay loop simulation problem with Icarus Verilog
fsm.finalize()
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