m-labs · Sep 12, 2015 · Sep 12, 2015 · Sep 12, 2015 · Sep 12, 2015
diff --git a/README.md b/README.md
@@ -47,7 +47,7 @@ http://m-labs.hk/gateware.html
 #### Quick intro
 
 ```python
-from migen.fhdl.std import *
+from migen import *
 from migen.build.platforms import m1
 plat = m1.Platform()
 led = plat.request("user_led")

diff --git a/doc/fhdl.rst b/doc/fhdl.rst
@@ -8,7 +8,7 @@ FHDL differs from MyHDL [myhdl]_ in fundamental ways. MyHDL follows the event-dr
 
 .. [myhdl] http://www.myhdl.org
 
-FHDL is made of several elements, which are briefly explained below. They all can be imported from the ``migen.fhdl.std`` module.
+FHDL is made of several elements, which are briefly explained below. They all can be imported directly from the ``migen`` module.
 
 Expressions
 ***********

diff --git a/examples/basic/arrays.py b/examples/basic/arrays.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -24,4 +24,5 @@ def __init__(self):
         outa = Array(Signal() for a in range(dy))
         self.specials += Instance("test", o_O=outa[y], i_I=ina[x])
 
-print(verilog.convert(Example()))
+if __name__ == "__main__":
+    print(verilog.convert(Example()))
diff --git a/examples/basic/fsm.py b/examples/basic/fsm.py
@@ -1,7 +1,5 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
-from migen.genlib.fsm import FSM, NextState, NextValue
-
 
 class Example(Module):
     def __init__(self):
@@ -26,5 +24,6 @@ def __init__(self):
         self.bl = myfsm.before_leaving("FOO")
         self.al = myfsm.after_leaving("FOO")
 
-example = Example()
-print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
+if __name__ == "__main__":
+    example = Example()
+    print(verilog.convert(example, {example.s, example.counter, example.be, example.ae, example.bl, example.al}))
diff --git a/examples/basic/graycounter.py b/examples/basic/graycounter.py
@@ -1,8 +1,7 @@
 from random import Random
 
-from migen.fhdl.std import *
+from migen import *
 from migen.genlib.cdc import GrayCounter
-from migen.sim import Simulator
 
 
 def tb(dut):

diff --git a/examples/basic/instance.py b/examples/basic/instance.py
@@ -1,7 +1,6 @@
 import subprocess
 
-from migen.fhdl.std import *
-from migen.fhdl.specials import Instance
+from migen import *
 from migen.fhdl.verilog import convert
 
 

diff --git a/examples/basic/local_cd.py b/examples/basic/local_cd.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 from migen.genlib.divider import Divider
 
@@ -14,5 +14,6 @@ def __init__(self):
         self.submodules.foo = CDM()
         self.submodules.bar = CDM()
 
-mm = MultiMod()
-print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
+if __name__ == "__main__":
+    mm = MultiMod()
+    print(verilog.convert(mm, {mm.foo.cd_sys.clk, mm.bar.cd_sys.clk}))
diff --git a/examples/basic/memory.py b/examples/basic/memory.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -11,5 +11,7 @@ def __init__(self):
         self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
             p2.adr, p2.dat_r, p2.re}
 
-example = Example()
-print(verilog.convert(example, example.ios))
+
+if __name__ == "__main__":
+    example = Example()
+    print(verilog.convert(example, example.ios))
diff --git a/examples/basic/namer.py b/examples/basic/namer.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 from functools import reduce

diff --git a/examples/basic/psync.py b/examples/basic/psync.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl.specials import SynthesisDirective
 from migen.fhdl import verilog
 from migen.genlib.cdc import *
@@ -16,6 +16,8 @@ class XilinxMultiReg:
     def lower(dr):
         return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
 
-ps = PulseSynchronizer("from", "to")
-v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
-print(v)
+
+if __name__ == "__main__":
+    ps = PulseSynchronizer("from", "to")
+    v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
+    print(v)
diff --git a/examples/basic/record.py b/examples/basic/record.py
@@ -1,6 +1,6 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
-from migen.genlib.record import *
+
 
 L = [
     ("position", [
@@ -19,6 +19,8 @@ def __init__(self):
         slave = Record(L)
         self.comb += master.connect(slave)
 
-print(verilog.convert(Test()))
-print(layout_len(L))
-print(layout_partial(L, "position/x", "color"))
+
+if __name__ == "__main__":
+    print(verilog.convert(Test()))
+    print(layout_len(L))
+    print(layout_partial(L, "position/x", "color"))
diff --git a/examples/basic/reslice.py b/examples/basic/reslice.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -14,4 +14,6 @@ def __init__(self):
         self.comb += s3.eq(0)
         self.comb += d.eq(Cat(d[::-1], Cat(s1[:1], s3[-4:])[:3]))
 
-print(verilog.convert(Example()))
+
+if __name__ == "__main__":
+    print(verilog.convert(Example()))
diff --git a/examples/basic/tristate.py b/examples/basic/tristate.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 
 
@@ -8,5 +8,6 @@ def __init__(self, n=6):
         self.t = TSTriple(n)
         self.specials += self.t.get_tristate(self.pad)
 
-e = Example()
-print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
+if __name__ == "__main__":
+    e = Example()
+    print(verilog.convert(e, ios={e.pad, e.t.o, e.t.oe, e.t.i}))
diff --git a/examples/basic/two_dividers.py b/examples/basic/two_dividers.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
 from migen.genlib import divider
 
@@ -14,5 +14,6 @@ def __init__(self, width):
             d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
             d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}
 
-example = Example(16)
-print(verilog.convert(example, example.ios | {example.ce, example.reset}))
+if __name__ == "__main__":
+    example = Example(16)
+    print(verilog.convert(example, example.ios | {example.ce, example.reset}))
diff --git a/examples/sim/basic1.py b/examples/sim/basic1.py
@@ -1,5 +1,4 @@
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
 
 
 # Our simple counter, which increments at every cycle.

diff --git a/examples/sim/basic2.py b/examples/sim/basic2.py
@@ -1,5 +1,4 @@
-from migen.fhdl.std import *
-from migen.sim import Simulator
+from migen import *
 
 
 # A slightly more elaborate counter.

diff --git a/examples/sim/fir.py b/examples/sim/fir.py
@@ -1,13 +1,13 @@
+from functools import reduce
+from operator import add
+
 from math import cos, pi
 from scipy import signal
 import matplotlib.pyplot as plt
 
-from migen.fhdl.std import *
+from migen import *
 from migen.fhdl import verilog
-from migen.sim import Simulator
 
-from functools import reduce
-from operator import add
 
 # A synthesizable FIR filter.
 class FIR(Module):

diff --git a/examples/sim/memory.py b/examples/sim/memory.py
@@ -1,5 +1,4 @@
-from migen.fhdl.std import *
-from migen.sim.generic import run_simulation
+from migen import *
 
 
 class Mem(Module):

diff --git a/migen/__init__.py b/migen/__init__.py
@@ -0,0 +1,10 @@
+from migen.fhdl.structure import *
+from migen.fhdl.module import *
+from migen.fhdl.specials import *
+from migen.fhdl.bitcontainer import *
+from migen.fhdl.decorators import *
+
+from migen.sim import *
+
+from migen.genlib.record import *
+from migen.genlib.fsm import *
diff --git a/migen/build/altera/common.py b/migen/build/altera/common.py
@@ -1,4 +1,5 @@
-from migen.fhdl.std import Instance, Module
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
 from migen.genlib.io import DifferentialInput, DifferentialOutput
 
 

diff --git a/migen/build/generic_platform.py b/migen/build/generic_platform.py
@@ -1,12 +1,11 @@
 import os
 import sys
 
-from migen.fhdl.std import Signal
+from migen.fhdl.structure import Signal
 from migen.genlib.record import Record
 from migen.genlib.io import CRG
 from migen.fhdl import verilog, edif
 from migen.util.misc import autotype
-
 from migen.build import tools
 
 

diff --git a/migen/build/lattice/common.py b/migen/build/lattice/common.py
@@ -1,6 +1,6 @@
-from migen.fhdl.std import *
+from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
 from migen.genlib.io import *
-
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 
@@ -36,6 +36,6 @@ def lower(dr):
         return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)
 
 lattice_special_overrides = {
-    AsyncResetSynchronizer:    LatticeAsyncResetSynchronizer,
-    DDROutput:    LatticeDDROutput
+    AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
+    DDROutput: LatticeDDROutput
 }
diff --git a/migen/build/sim/verilator.py b/migen/build/sim/verilator.py
@@ -4,18 +4,14 @@
 import os
 import subprocess
 
-from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-
 from migen.build import tools
 from migen.build.generic_platform import *
-from migen.build.sim import common
 
 
 def _build_tb(platform, vns, serial, template):
-
-    def io_name(ressource, subsignal=None):
-        res = platform.lookup_request(ressource)
+    def io_name(resource, subsignal=None):
+        res = platform.lookup_request(resource)
         if subsignal is not None:
             res = getattr(res, subsignal)
         return vns.get_name(res)

diff --git a/migen/build/xilinx/common.py b/migen/build/xilinx/common.py
@@ -2,7 +2,9 @@
 import sys
 from distutils.version import StrictVersion
 
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
+from migen.fhdl.specials import Instance
+from migen.fhdl.module import Module
 from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer

diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py
@@ -2,7 +2,6 @@
 import subprocess
 import sys
 
-from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
 from migen.build.generic_platform import *
 from migen.build import tools

diff --git a/migen/build/xilinx/vivado.py b/migen/build/xilinx/vivado.py
@@ -5,9 +5,7 @@
 import subprocess
 import sys
 
-from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
-
 from migen.build.generic_platform import *
 from migen.build import tools
 from migen.build.xilinx import common

diff --git a/migen/fhdl/bitcontainer.py b/migen/fhdl/bitcontainer.py
@@ -1,6 +1,9 @@
 from migen.fhdl import structure as f
 
 
+__all__ = ["log2_int", "bits_for", "flen", "fiter", "fslice", "freversed"]
+
+
 def log2_int(n, need_pow2=True):
     l = 1
     r = 0

diff --git a/migen/fhdl/decorators.py b/migen/fhdl/decorators.py
@@ -1,10 +1,14 @@
-import warnings
-
 from migen.fhdl.structure import *
 from migen.fhdl.module import Module
 from migen.fhdl.tools import insert_reset, rename_clock_domain
 
 
+__all__ = ["DecorateModule",
+           "InsertCE", "InsertReset", "RenameClockDomains",
+           "CEInserter", "ResetInserter", "ClockDomainsRenamer",
+           "ModuleTransformer"]
+
+
 class ModuleTransformer:
     # overload this in derived classes
     def transform_instance(self, i):
@@ -47,16 +51,6 @@ def __call__(self, victim):
         else:
             return self.wrap_class(victim)
 
-    @classmethod
-    def adhoc(cls, i, *args, **kwargs):
-        warnings.warn("deprecated, use the plain transformer", DeprecationWarning, 2)
-        return cls(*args, **kwargs)(i)
-
-
-def DecorateModule(transformer, *args, **kwargs):
-    warnings.warn("deprecated, use the plain transformer", DeprecationWarning, 2)
-    return transformer.__self__(*args, **kwargs)
-
 
 class ControlInserter(ModuleTransformer):
     control_name = None  # override this

diff --git a/migen/fhdl/edif.py b/migen/fhdl/edif.py
@@ -1,7 +1,6 @@
-from collections import OrderedDict
-from collections import namedtuple
+from collections import OrderedDict, namedtuple
 
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
 from migen.fhdl.namer import build_namespace
 from migen.fhdl.tools import list_special_ios
 from migen.fhdl.structure import _Fragment

diff --git a/migen/fhdl/module.py b/migen/fhdl/module.py
@@ -7,6 +7,9 @@
 from migen.fhdl.tools import rename_clock_domain
 
 
+__all__ = ["Module", "FinalizeError"]
+
+
 class FinalizeError(Exception):
     pass
 

diff --git a/migen/fhdl/simplify.py b/migen/fhdl/simplify.py
@@ -1,4 +1,4 @@
-from migen.fhdl.std import *
+from migen.fhdl.structure import *
 from migen.fhdl.specials import _MemoryPort
 from migen.fhdl.decorators import ModuleTransformer
 from migen.util.misc import gcd_multiple