m-labs · Sep 12, 2015 · Sep 12, 2015 · Sep 12, 2015 · Sep 12, 2015 · Sep 12, 2015
Showing with 72 additions and 91 deletions.

+10 −11 examples/basic/graycounter.py

+0 −1 migen/genlib/sort.py

+33 −23 migen/sim.py

+3 −13 migen/test/support.py

+1 −17 migen/test/test_examples.py

+15 −19 migen/test/test_signed.py

+10 −7 migen/test/test_sort.py
diff --git a/examples/basic/graycounter.py b/examples/basic/graycounter.py
@@ -2,19 +2,18 @@
 
 from migen.fhdl.std import *
 from migen.genlib.cdc import GrayCounter
-from migen.sim.generic import run_simulation
+from migen.sim import Simulator
 
 
-class TB(Module):
-    def __init__(self, width=3):
-        self.width = width
-        self.submodules.gc = GrayCounter(self.width)
-        self.prng = Random(7345)
+def tb(dut):
+    prng = Random(7345)
+    for i in range(35):
+        print("{0:0{1}b} CE={2} bin={3}".format((yield dut.q),
+            flen(dut.q), (yield dut.ce), (yield dut.q_binary)))
+        yield dut.ce, prng.getrandbits(1)
+        yield
 
-    def do_simulation(self, selfp):
-        print("{0:0{1}b} CE={2} bin={3}".format(selfp.gc.q,
-            self.width, selfp.gc.ce, selfp.gc.q_binary))
-        selfp.gc.ce = self.prng.getrandbits(1)
 
 if __name__ == "__main__":
-    run_simulation(TB(), ncycles=35)
+    dut = GrayCounter(3)
+    Simulator(dut, tb(dut)).run()
diff --git a/migen/genlib/sort.py b/migen/genlib/sort.py
@@ -1,5 +1,4 @@
 from migen.fhdl.std import *
-from migen.fhdl import verilog
 
 
 class BitonicSort(Module):

diff --git a/migen/sim.py b/migen/sim.py
@@ -141,46 +141,56 @@ def __init__(self, fragment_or_module, generators, clocks={"sys": 100}):
             for signal in list_inputs(statement):
                 self.comb_dependent_statements[signal].append(statement)
 
-    def _comb_propagate(self, modified):
+    def _commit_and_comb_propagate(self):
+        modified = self.evaluator.commit()
         while modified:
             for signal in modified:
                 self.evaluator.execute(self.comb_dependent_statements[signal])
             modified = self.evaluator.commit()
 
+    def _eval_nested_lists(self, x):
+        if isinstance(x, list):
+            return [self._eval_nested_lists(e) for e in x]
+        elif isinstance(x, Signal):
+            return self.evaluator.eval(x)
+        else:
+            raise ValueError
+
     def _process_generators(self, cd):
-        if cd in self.generators:
-            exhausted = []
-            for generator in self.generators[cd]:
-                reply = None
-                while True:
-                    try:
-                        request = generator.send(reply)
-                        if request is None:
-                            break  # next cycle
-                        elif isinstance(request, tuple):
-                            self.evaluator.assign(*request)
-                        else:
-                            reply = self.evaluator.eval(request)
-                    except StopIteration:
-                        exhausted.append(generator)
-                        break
-            for generator in exhausted:
-                self.generators[cd].remove(generator)
+        exhausted = []
+        for generator in self.generators[cd]:
+            reply = None
+            while True:
+                try:
+                    request = generator.send(reply)
+                    if request is None:
+                        break  # next cycle
+                    elif isinstance(request, tuple):
+                        self.evaluator.assign(*request)
+                    else:
+                        reply = self._eval_nested_lists(request)
+                except StopIteration:
+                    exhausted.append(generator)
+                    break
+        for generator in exhausted:
+            self.generators[cd].remove(generator)
 
     def _continue_simulation(self):
         # TODO: passive generators
         return any(self.generators.values())
 
     def run(self):
         self.evaluator.execute(self.fragment.comb)
-        self._comb_propagate(self.evaluator.commit())
+        self._commit_and_comb_propagate()
 
         while True:
             cds = self.time.tick()
             for cd in cds:
-                self.evaluator.execute(self.fragment.sync[cd])
-                self._process_generators(cd)
-            self._comb_propagate(self.evaluator.commit())
+                if cd in self.fragment.sync:
+                    self.evaluator.execute(self.fragment.sync[cd])
+                if cd in self.generators:
+                    self._process_generators(cd)
+            self._commit_and_comb_propagate()
 
             if not self._continue_simulation():
                 break
diff --git a/migen/test/support.py b/migen/test/support.py
@@ -1,24 +1,14 @@
 from migen.fhdl.std import *
-from migen.sim.generic import run_simulation
+from migen.sim import Simulator
 from migen.fhdl import verilog
 
 
-class SimBench(Module):
-    callback = None
-    def do_simulation(self, selfp):
-        if self.callback is not None:
-            return self.callback(self, selfp)
-
-
 class SimCase:
-    TestBench = SimBench
-
     def setUp(self, *args, **kwargs):
         self.tb = self.TestBench(*args, **kwargs)
 
     def test_to_verilog(self):
         verilog.convert(self.tb)
 
-    def run_with(self, cb, ncycles=None):
-        self.tb.callback = cb
-        run_simulation(self.tb, ncycles=ncycles)
+    def run_with(self, generator):
+        Simulator(self.tb, generator).run()
diff --git a/migen/test/test_examples.py b/migen/test/test_examples.py
@@ -21,10 +21,8 @@ def test_method(self):
 class TestExamplesSim(unittest.TestCase):
     pass
 
-for name in ("abstract_transactions_wb",
-              "basic1",
+for name in ("basic1",
               "basic2",
-              "dataflow",
               # skip "fir" as it depends on SciPy
               # "fir",
               "memory"):
@@ -36,30 +34,16 @@ class TestExamplesBasic(unittest.TestCase):
     pass
 
 for name in ("arrays",
-              "complex",
               "fsm",
               "graycounter",
-              "hamming",
               "local_cd",
               "memory",
               "namer",
               "psync",
               "record",
               "reslice",
-              "simple_gpio",
               "tristate",
               "two_dividers"):
     setattr(TestExamplesBasic, "test_" + name,
             _make_test_method(name, "basic"))
 
-
-class TestDataflow(unittest.TestCase):
-    pass
-
-for name in ("dma",
-              "misc",
-              # skip "structuring" as it depends on networkx, SciPy
-              # "structuring",
-              ):
-    setattr(TestDataflow, "test_" + name,
-            _make_test_method(name, "dataflow"))
diff --git a/migen/test/test_signed.py b/migen/test/test_signed.py
@@ -1,11 +1,11 @@
 import unittest
 
 from migen.fhdl.std import *
-from migen.test.support import SimCase, SimBench
+from migen.test.support import SimCase
 
 
 class SignedCase(SimCase, unittest.TestCase):
-    class TestBench(SimBench):
+    class TestBench(Module):
         def __init__(self):
             self.a = Signal((3, True))
             self.b = Signal((4, True))
@@ -27,20 +27,16 @@ def __init__(self):
                         self.vals.append((asign, bsign, f, r, r0.op))
 
     def test_comparisons(self):
-        values = range(-4, 4)
-        agen = iter(values)
-        bgen = iter(values)
-        def cb(tb, tbp):
-            try:
-                tbp.a = next(agen)
-                tbp.b = next(bgen)
-            except StopIteration:
-                raise StopSimulation
-            a = tbp.a
-            b = tbp.b
-            for asign, bsign, f, r, op in self.tb.vals:
-                r, r0 = tbp.simulator.rd(r), f(asign*a, bsign*b)
-                self.assertEqual(r, int(r0),
-                        "got {}, want {}*{} {} {}*{} = {}".format(
-                            r, asign, a, op, bsign, b, r0))
-        self.run_with(cb)
+        def gen():
+            for i in range(-4, 4):
+                yield self.tb.a, i
+                yield self.tb.b, i
+                a = yield self.tb.a
+                b = yield self.tb.b
+                for asign, bsign, f, r, op in self.tb.vals:
+                    r, r0 = (yield r), f(asign*a, bsign*b)
+                    self.assertEqual(r, int(r0),
+                            "got {}, want {}*{} {} {}*{} = {}".format(
+                                r, asign, a, op, bsign, b, r0))
+                yield
+        self.run_with(gen())
diff --git a/migen/test/test_sort.py b/migen/test/test_sort.py
@@ -4,11 +4,11 @@
 from migen.fhdl.std import *
 from migen.genlib.sort import *
 
-from migen.test.support import SimCase, SimBench
+from migen.test.support import SimCase
 
 
 class BitonicCase(SimCase, unittest.TestCase):
-    class TestBench(SimBench):
+    class TestBench(Module):
         def __init__(self):
             self.submodules.dut = BitonicSort(8, 4, ascending=True)
 
@@ -20,8 +20,11 @@ def test_sizes(self):
             self.assertEqual(flen(self.tb.dut.o[i]), 4)
 
     def test_sort(self):
-        def cb(tb, tbp):
-            for i in tb.dut.i:
-                tbp.simulator.wr(i, randrange(1<<flen(i)))
-            self.assertEqual(sorted(list(tbp.dut.i)), list(tbp.dut.o))
-        self.run_with(cb, 20)
+        def gen():
+            for repeat in range(20):
+                for i in self.tb.dut.i:
+                    yield i, randrange(1<<flen(i))
+                yield
+                self.assertEqual(sorted((yield self.tb.dut.i)),
+                                 (yield self.tb.dut.o))
+        self.run_with(gen())