dvisampler/edid: fix sda sampling, needs to be similar to scl.

Video sources with high scl frequency were not able to access EDID information through I2C. I2C start was not detected correctly and was randomly reseting the fsm during transfers.(seen with litescope)
m-labs · Sep 10, 2015 · 31956de · 31956de
1 parent 12f5858
commit 31956de
Showing 1 changed file with 6 additions and 2 deletions.
diff --git a/misoclib/video/dvisampler/edid.py b/misoclib/video/dvisampler/edid.py
@@ -36,22 +36,26 @@ def __init__(self, pads, default=_default_edid):
         # EDID
         scl_raw = Signal()
         sda_i = Signal()
+        sda_raw = Signal()
         sda_drv = Signal()
         _sda_drv_reg = Signal()
         _sda_i_async = Signal()
         self.sync += _sda_drv_reg.eq(sda_drv)
         self.specials += [
             MultiReg(pads.scl, scl_raw),
             Tristate(pads.sda, 0, _sda_drv_reg, _sda_i_async),
-            MultiReg(_sda_i_async, sda_i)
+            MultiReg(_sda_i_async, sda_raw)
         ]
 
         scl_i = Signal()
         samp_count = Signal(6)
         samp_carry = Signal()
         self.sync += [
             Cat(samp_count, samp_carry).eq(samp_count + 1),
-            If(samp_carry, scl_i.eq(scl_raw))
+            If(samp_carry,
+                scl_i.eq(scl_raw),
+                sda_i.eq(sda_raw)
+            )
         ]
 
         scl_r = Signal()