m-labs · Sep 11, 2015 · Sep 11, 2015 · Sep 11, 2015 · Sep 11, 2015 · Sep 11, 2015
diff --git a/examples/sim/abstract_transactions_wb.py b/examples/sim/abstract_transactions_wb.py
diff --git a/examples/sim/basic1.py b/examples/sim/basic1.py
@@ -1,9 +1,8 @@
 from migen.fhdl.std import *
-from migen.sim.generic import run_simulation
+from migen.sim import Simulator
 
 
-# Our simple counter, which increments at every cycle
-# and prints its current value in simulation.
+# Our simple counter, which increments at every cycle.
 class Counter(Module):
     def __init__(self):
         self.count = Signal(4)
@@ -12,18 +11,20 @@ def __init__(self):
         # We do it with convertible/synthesizable FHDL code.
         self.sync += self.count.eq(self.count + 1)
 
-    # This function will be called at every cycle.
-    def do_simulation(self, selfp):
-        # Simply read the count signal and print it.
-        # The output is:
-        # Count: 0
-        # Count: 1
-        # Count: 2
-        # ...
-        print("Count: " + str(selfp.count))
+
+# Simply read the count signal and print it.
+# The output is:
+# Count: 0
+# Count: 1
+# Count: 2
+# ...
+def counter_test(dut):
+    for i in range(20):
+        print((yield dut.count))  # read and print
+        yield  # next clock cycle
+    # simulation ends with this generator
+
 
 if __name__ == "__main__":
     dut = Counter()
-    # Since we do not use StopSimulation, limit the simulation
-    # to some number of cycles.
-    run_simulation(dut, ncycles=20)
+    Simulator(dut, counter_test(dut)).run()
diff --git a/examples/sim/basic2.py b/examples/sim/basic2.py
@@ -1,5 +1,5 @@
 from migen.fhdl.std import *
-from migen.sim.generic import run_simulation
+from migen.sim import Simulator
 
 
 # A slightly more elaborate counter.
@@ -13,15 +13,17 @@ def __init__(self):
 
         self.sync += If(self.ce, self.count.eq(self.count + 1))
 
-    def do_simulation(self, selfp):
+
+def counter_test(dut):
+    for cycle in range(20):
         # Only assert CE every second cycle.
         # => each counter value is held for two cycles.
-        if selfp.simulator.cycle_counter % 2:
-            selfp.ce = 0  # This is how you write to a signal.
+        if cycle % 2:
+            yield dut.ce, 0  # This is how you write to a signal.
         else:
-            selfp.ce = 1
-        print("Cycle: " + str(selfp.simulator.cycle_counter) + " Count: " + \
-            str(selfp.count))
+            yield dut.ce, 1
+        print("Cycle: {} Count: {}".format(cycle, (yield dut.count)))
+        yield
 
 # Output is:
 # Cycle: 0 Count: -5
@@ -33,5 +35,4 @@ def do_simulation(self, selfp):
 
 if __name__ == "__main__":
     dut = Counter()
-    # Demonstrate VCD output
-    run_simulation(dut, vcd_name="my.vcd", ncycles=20)
+    Simulator(dut, counter_test(dut)).run()
diff --git a/examples/sim/dataflow.py b/examples/sim/dataflow.py
diff --git a/examples/sim/fir.py b/examples/sim/fir.py
@@ -4,7 +4,7 @@
 
 from migen.fhdl.std import *
 from migen.fhdl import verilog
-from migen.sim.generic import run_simulation
+from migen.sim import Simulator
 
 from functools import reduce
 from operator import add
@@ -29,24 +29,20 @@ def __init__(self, coef, wsize=16):
             muls.append(c_fp*sreg)
         sum_full = Signal((2*self.wsize-1, True))
         self.sync += sum_full.eq(reduce(add, muls))
-        self.comb += self.o.eq(sum_full[self.wsize-1:])
+        self.comb += self.o.eq(sum_full >> self.wsize-1)
 
 
 # A test bench for our FIR filter.
 # Generates a sine wave at the input and records the output.
-class TB(Module):
-    def __init__(self, coef, frequency):
-        self.submodules.fir = FIR(coef)
-        self.frequency = frequency
-        self.inputs = []
-        self.outputs = []
+def fir_tb(dut, frequency, inputs, outputs):
+    f = 2**(dut.wsize - 1)
+    for cycle in range(200):
+        v = 0.1*cos(2*pi*frequency*cycle)
+        yield dut.i, int(f*v)
+        inputs.append(v)
+        outputs.append((yield dut.o)/f)
+        yield
 
-    def do_simulation(self, selfp):
-        f = 2**(self.fir.wsize - 1)
-        v = 0.1*cos(2*pi*self.frequency*selfp.simulator.cycle_counter)
-        selfp.fir.i = int(f*v)
-        self.inputs.append(v)
-        self.outputs.append(selfp.fir.o/f)
 
 if __name__ == "__main__":
     # Compute filter coefficients with SciPy.
@@ -57,10 +53,9 @@ def do_simulation(self, selfp):
     in_signals = []
     out_signals = []
     for frequency in [0.05, 0.1, 0.25]:
-        tb = TB(coef, frequency)
-        run_simulation(tb, ncycles=200)
-        in_signals += tb.inputs
-        out_signals += tb.outputs
+        dut = FIR(coef)
+        tb = fir_tb(dut, frequency, in_signals, out_signals)
+        Simulator(dut, tb).run()
 
     # Plot data from the input and output waveforms.
     plt.plot(in_signals)

diff --git a/migen/fhdl/module.py b/migen/fhdl/module.py
@@ -5,7 +5,6 @@
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Fragment
 from migen.fhdl.tools import rename_clock_domain
-from migen.sim.upper import gen_sim, proxy_sim
 
 
 class FinalizeError(Exception):
@@ -118,20 +117,7 @@ def __getattr__(self, name):
             self.finalized = False
             return self.finalized
         elif name == "_fragment":
-            simf = None
-            try:
-                simf = self.do_simulation
-            except AttributeError:
-                try:
-                    simg = self.gen_simulation
-                except AttributeError:
-                    pass
-                else:
-                    simf = gen_sim(simg)
-            if simf is not None:
-                simf = proxy_sim(self, simf)
-            sim = [] if simf is None else [simf]
-            self._fragment = _Fragment(sim=sim)
+            self._fragment = _Fragment()
             return self._fragment
         elif name == "_submodules":
             self._submodules = []

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
@@ -572,23 +572,17 @@ def __getitem__(self, key):
 (SPECIAL_INPUT, SPECIAL_OUTPUT, SPECIAL_INOUT) = range(3)
 
 
-class StopSimulation(Exception):
-    pass
-
-
 class _Fragment:
-    def __init__(self, comb=None, sync=None, specials=None, clock_domains=None, sim=None):
+    def __init__(self, comb=None, sync=None, specials=None, clock_domains=None):
         if comb is None: comb = []
         if sync is None: sync = dict()
         if specials is None: specials = set()
         if clock_domains is None: clock_domains = _ClockDomainList()
-        if sim is None: sim = []
 
         self.comb = comb
         self.sync = sync
         self.specials = specials
         self.clock_domains = _ClockDomainList(clock_domains)
-        self.sim = sim
 
     def __add__(self, other):
         newsync = defaultdict(list)
@@ -598,8 +592,7 @@ def __add__(self, other):
             newsync[k].extend(v)
         return _Fragment(self.comb + other.comb, newsync,
             self.specials | other.specials,
-            self.clock_domains + other.clock_domains,
-            self.sim + other.sim)
+            self.clock_domains + other.clock_domains)
 
     def __iadd__(self, other):
         newsync = defaultdict(list)
@@ -611,5 +604,4 @@ def __iadd__(self, other):
         self.sync = newsync
         self.specials |= other.specials
         self.clock_domains += other.clock_domains
-        self.sim += other.sim
         return self
diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
@@ -32,6 +32,17 @@ def visit_ArrayProxy(self, node):
             self.visit(choice)
 
 
+class _InputLister(NodeVisitor):
+    def __init__(self):
+        self.output_list = set()
+
+    def visit_Signal(self, node):
+        self.output_list.add(node)
+
+    def visit_Assign(self, node):
+        self.visit(node.r)
+
+
 def list_signals(node):
     lister = _SignalLister()
     lister.visit(node)
@@ -44,6 +55,12 @@ def list_targets(node):
     return lister.output_list
 
 
+def list_inputs(node):
+    lister = _InputLister()
+    lister.visit(node)
+    return lister.output_list
+
+
 def _resort_statements(ol):
     return [statement for i, statement in
             sorted(ol, key=lambda x: x[0])]