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sbourdeauducqsbourdeauducq
committedSep 15, 2015
fhdl/structure: introduce Constant, autowrap for eq/ops, fix Signal as dictionary key problem
·
0.9.20.2
1 parent 42afba2 commit e940c6d

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7 files changed

+224
-108
lines changed

7 files changed

+224
-108
lines changed
 

Diff for: ‎migen/fhdl/bitcontainer.py

+1-5
Original file line numberDiff line numberDiff line change
@@ -27,11 +27,7 @@ def bits_for(n, require_sign_bit=False):
2727

2828

2929
def value_bits_sign(v):
30-
if isinstance(v, bool):
31-
return 1, False
32-
elif isinstance(v, int):
33-
return bits_for(v), v < 0
34-
elif isinstance(v, f.Signal):
30+
if isinstance(v, (f.Constant, f.Signal)):
3531
return v.nbits, v.signed
3632
elif isinstance(v, (f.ClockSignal, f.ResetSignal)):
3733
return 1, False

Diff for: ‎migen/fhdl/namer.py

+6-6
Original file line numberDiff line numberDiff line change
@@ -158,16 +158,16 @@ def _build_pnd_for_group(group_n, signals):
158158
if _debug:
159159
print("namer: using basic strategy (group {0})".format(group_n))
160160

161-
# ...then add number suffixes by HUID
161+
# ...then add number suffixes by DUID
162162
inv_pnd = _invert_pnd(pnd)
163-
huid_suffixed = False
163+
duid_suffixed = False
164164
for name, signals in inv_pnd.items():
165165
if len(signals) > 1:
166-
huid_suffixed = True
167-
for n, signal in enumerate(sorted(signals, key=lambda x: x.huid)):
166+
duid_suffixed = True
167+
for n, signal in enumerate(sorted(signals, key=lambda x: x.duid)):
168168
pnd[signal] += str(n)
169-
if _debug and huid_suffixed:
170-
print("namer: using HUID suffixes (group {0})".format(group_n))
169+
if _debug and duid_suffixed:
170+
print("namer: using DUID suffixes (group {0})".format(group_n))
171171

172172
return pnd
173173

Diff for: ‎migen/fhdl/specials.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
from operator import itemgetter
22

33
from migen.fhdl.structure import *
4+
from migen.fhdl.structure import _DUID
45
from migen.fhdl.bitcontainer import bits_for, value_bits_sign
56
from migen.fhdl.tools import *
67
from migen.fhdl.tracer import get_obj_var_name
@@ -11,7 +12,7 @@
1112
"READ_FIRST", "WRITE_FIRST", "NO_CHANGE"]
1213

1314

14-
class Special(HUID):
15+
class Special(_DUID):
1516
def iter_expressions(self):
1617
for x in []:
1718
yield x

Diff for: ‎migen/fhdl/structure.py

+181-55
Large diffs are not rendered by default.

Diff for: ‎migen/fhdl/tools.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -143,7 +143,7 @@ def is_variable(node):
143143

144144
def generate_reset(rst, sl):
145145
targets = list_targets(sl)
146-
return [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.huid)]
146+
return [t.eq(t.reset) for t in sorted(targets, key=lambda x: x.duid)]
147147

148148

149149
def insert_reset(rst, sl):

Diff for: ‎migen/fhdl/verilog.py

+31-38
Original file line numberDiff line numberDiff line change
@@ -10,23 +10,24 @@
1010

1111

1212
_reserved_keywords = {
13-
"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
14-
"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
15-
"defparam", "design", "disable", "edge", "else", "end", "endcase", "endconfig",
16-
"endfunction", "endgenerate", "endmodule", "endprimitive", "endspecify",
17-
"endtable", "endtask", "event", "for", "force", "forever", "fork", "function",
18-
"generate", "genvar", "highz0", "highz1", "if", "ifnone", "incdir", "include",
19-
"initial", "inout", "input", "instance", "integer", "join", "large", "liblist",
20-
"library", "localparam", "macromodule", "medium", "module", "nand", "negedge",
21-
"nmos", "nor", "noshowcancelled", "not", "notif0", "notif1", "or", "output",
22-
"parameter", "pmos", "posedge", "primitive", "pull0", "pull1" "pulldown"
23-
"pullup","pulsestyle_onevent", "pulsestyle_ondetect", "remos", "real",
24-
"realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran", "rtranif0",
25-
"rtranif1", "scalared", "showcancelled", "signed", "small", "specify",
26-
"specparam", "strong0", "strong1", "supply0", "supply1", "table", "task",
27-
"time", "tran", "tranif0", "tranif1", "tri", "tri0", "tri1", "triand",
28-
"trior", "trireg", "unsigned", "use", "vectored", "wait", "wand", "weak0",
29-
"weak1", "while", "wire", "wor","xnor","xor"
13+
"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
14+
"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
15+
"defparam", "design", "disable", "edge", "else", "end", "endcase",
16+
"endconfig", "endfunction", "endgenerate", "endmodule", "endprimitive",
17+
"endspecify", "endtable", "endtask", "event", "for", "force", "forever",
18+
"fork", "function", "generate", "genvar", "highz0", "highz1", "if",
19+
"ifnone", "incdir", "include", "initial", "inout", "input",
20+
"instance", "integer", "join", "large", "liblist", "library", "localparam",
21+
"macromodule", "medium", "module", "nand", "negedge", "nmos", "nor",
22+
"noshowcancelled", "not", "notif0", "notif1", "or", "output", "parameter",
23+
"pmos", "posedge", "primitive", "pull0", "pull1" "pulldown",
24+
"pullup", "pulsestyle_onevent", "pulsestyle_ondetect", "remos", "real",
25+
"realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran",
26+
"rtranif0", "rtranif1", "scalared", "showcancelled", "signed", "small",
27+
"specify", "specparam", "strong0", "strong1", "supply0", "supply1",
28+
"table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
29+
"tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
30+
"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor"
3031
}
3132

3233

@@ -41,25 +42,17 @@ def _printsig(ns, s):
4142
return n
4243

4344

44-
def _printintbool(node):
45-
if isinstance(node, bool):
46-
if node:
47-
return "1'd1", False
48-
else:
49-
return "1'd0", False
50-
elif isinstance(node, int):
51-
nbits = bits_for(node)
52-
if node >= 0:
53-
return str(nbits) + "'d" + str(node), False
54-
else:
55-
return str(nbits) + "'sd" + str(2**nbits + node), True
45+
def _printconstant(node):
46+
if node.signed:
47+
return (str(node.nbits) + "'sd" + str(2**node.nbits + node.value),
48+
True)
5649
else:
57-
raise TypeError
50+
return str(node.nbits) + "'d" + str(node.value), False
5851

5952

6053
def _printexpr(ns, node):
61-
if isinstance(node, (int, bool)):
62-
return _printintbool(node)
54+
if isinstance(node, Constant):
55+
return _printconstant(node)
6356
elif isinstance(node, Signal):
6457
return ns.get_name(node), node.signed
6558
elif isinstance(node, _Operator):
@@ -116,7 +109,7 @@ def _printexpr(ns, node):
116109
elif isinstance(node, Replicate):
117110
return "{" + str(node.n) + "{" + _printexpr(ns, node.v)[0] + "}}", False
118111
else:
119-
raise TypeError("Expression of unrecognized type: "+str(type(node)))
112+
raise TypeError("Expression of unrecognized type: '{}'".format(type(node).__name__))
120113

121114

122115
(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
@@ -148,7 +141,7 @@ def _printnode(ns, at, level, node):
148141
elif isinstance(node, Case):
149142
if node.cases:
150143
r = "\t"*level + "case (" + _printexpr(ns, node.test)[0] + ")\n"
151-
css = sorted([(k, v) for (k, v) in node.cases.items() if k != "default"], key=itemgetter(0))
144+
css = sorted([(k, v) for (k, v) in node.cases.items() if isinstance(k, Constant)], key=itemgetter(0))
152145
for choice, statements in css:
153146
r += "\t"*(level + 1) + _printexpr(ns, choice)[0] + ": begin\n"
154147
r += _printnode(ns, at, level + 2, statements)
@@ -183,7 +176,7 @@ def _printheader(f, ios, name, ns,
183176
wires = _list_comb_wires(f) | special_outs
184177
r = "module " + name + "(\n"
185178
firstp = True
186-
for sig in sorted(ios, key=lambda x: x.huid):
179+
for sig in sorted(ios, key=lambda x: x.duid):
187180
if not firstp:
188181
r += ",\n"
189182
firstp = False
@@ -197,7 +190,7 @@ def _printheader(f, ios, name, ns,
197190
else:
198191
r += "\tinput " + _printsig(ns, sig)
199192
r += "\n);\n\n"
200-
for sig in sorted(sigs - ios, key=lambda x: x.huid):
193+
for sig in sorted(sigs - ios, key=lambda x: x.duid):
201194
if sig in wires:
202195
r += "wire " + _printsig(ns, sig) + ";\n"
203196
else:
@@ -280,7 +273,7 @@ def _call_special_classmethod(overrides, obj, method, *args, **kwargs):
280273
def _lower_specials_step(overrides, specials):
281274
f = _Fragment()
282275
lowered_specials = set()
283-
for special in sorted(specials, key=lambda x: x.huid):
276+
for special in sorted(specials, key=lambda x: x.duid):
284277
impl = _call_special_classmethod(overrides, special, "lower")
285278
if impl is not None:
286279
f += impl.get_fragment()
@@ -310,7 +303,7 @@ def _lower_specials(overrides, specials):
310303

311304
def _printspecials(overrides, specials, ns, add_data_file):
312305
r = ""
313-
for special in sorted(specials, key=lambda x: x.huid):
306+
for special in sorted(specials, key=lambda x: x.duid):
314307
pr = _call_special_classmethod(overrides, special, "emit_verilog", ns, add_data_file)
315308
if pr is None:
316309
raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")

Diff for: ‎migen/sim.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -73,8 +73,8 @@ def commit(self):
7373
return r
7474

7575
def eval(self, node):
76-
if isinstance(node, (int, bool)):
77-
return node
76+
if isinstance(node, Constant):
77+
return node.value
7878
elif isinstance(node, Signal):
7979
try:
8080
return self.signal_values[node]

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