litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow)

enjoy-digital · enjoy-digital · commit dfc207aacb32 · 2015-07-22T21:44:53.000+02:00
diff --git a/misoclib/com/litepcie/common.py b/misoclib/com/litepcie/common.py
@@ -63,5 +63,5 @@ def interrupt_layout():
 
 
 def dma_layout(dw):
-    layout = [("dat", dw)]
+    layout = [("data", dw)]
     return EndpointDescription(layout, packetized=True)
diff --git a/misoclib/com/litepcie/frontend/dma/reader.py b/misoclib/com/litepcie/frontend/dma/reader.py
@@ -70,7 +70,7 @@ def __init__(self, endpoint, port, table_depth=256):
         self.comb += [
             fifo.sink.stb.eq(port.sink.stb),
             fifo.sink.sop.eq(port.sink.sop & (port.sink.user_id != last_user_id)),
-            fifo.sink.dat.eq(port.sink.dat),
+            fifo.sink.data.eq(port.sink.dat),
             port.sink.ack.eq(fifo.sink.ack | ~enable),
         ]
         self.comb += Record.connect(fifo.source, self.source)
diff --git a/misoclib/com/litepcie/frontend/dma/writer.py b/misoclib/com/litepcie/frontend/dma/writer.py
@@ -28,7 +28,7 @@ def __init__(self, endpoint, port, table_depth=256):
         self.comb += [
             fifo.we.eq(sink.stb & enable),
             sink.ack.eq(fifo.writable & sink.stb & enable),
-            fifo.din.eq(sink.dat),
+            fifo.din.eq(sink.data),
             fifo.reset.eq(~enable)
         ]
 

Original file line number	Diff line number	Diff line change
`@@ -70,7 +70,7 @@ def __init__(self, endpoint, port, table_depth=256):`
`70`	`70`	`self.comb += [`
`71`	`71`	`fifo.sink.stb.eq(port.sink.stb),`
`72`	`72`	`fifo.sink.sop.eq(port.sink.sop & (port.sink.user_id != last_user_id)),`
`73`		`- fifo.sink.dat.eq(port.sink.dat),`
	`73`	`+ fifo.sink.data.eq(port.sink.dat),`
`74`	`74`	`port.sink.ack.eq(fifo.sink.ack \| ~enable),`
`75`	`75`	`]`
`76`	`76`	`self.comb += Record.connect(fifo.source, self.source)`
Original file line number	Diff line number	Diff line change
`@@ -28,7 +28,7 @@ def __init__(self, endpoint, port, table_depth=256):`
`28`	`28`	`self.comb += [`
`29`	`29`	`fifo.we.eq(sink.stb & enable),`
`30`	`30`	`sink.ack.eq(fifo.writable & sink.stb & enable),`
`31`		`- fifo.din.eq(sink.dat),`
	`31`	`+ fifo.din.eq(sink.data),`
`32`	`32`	`fifo.reset.eq(~enable)`
`33`	`33`	`]`
`34`	`34`