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- reintroduce RX/TX split (ease comprehension) - use FIFO wrapper function from Migen. - add tx_irq_condition and rx_irq_condition
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@@ -2,13 +2,13 @@ | |
from migen.bank.description import * | ||
from migen.bank.eventmanager import * | ||
from migen.genlib.record import Record | ||
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO | ||
from migen.actorlib.fifo import FIFO | ||
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class UART(Module, AutoCSR): | ||
def __init__(self, phy, | ||
tx_fifo_depth=16, | ||
rx_fifo_depth=16, | ||
tx_fifo_depth=16, tx_irq_condition="empty", | ||
rx_fifo_depth=16, rx_irq_condition="non-empty", | ||
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enjoy-digital
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phy_cd="sys"): | ||
self._rxtx = CSR(8) | ||
self._txfull = CSRStatus() | ||
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@@ -21,30 +21,37 @@ def __init__(self, phy, | |
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# # # | ||
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if phy_cd == "sys": | ||
tx_fifo = SyncFIFO([("data", 8)], tx_fifo_depth) | ||
rx_fifo = SyncFIFO([("data", 8)], rx_fifo_depth) | ||
# Generate TX IRQ when tx_fifo becomes empty | ||
tx_irq = tx_fifo.source.stb | ||
else: | ||
tx_fifo = ClockDomainsRenamer({"write": "sys", "read": phy_cd})( | ||
AsyncFIFO([("data", 8)], tx_fifo_depth)) | ||
rx_fifo = ClockDomainsRenamer({"write": phy_cd, "read": "sys"})( | ||
AsyncFIFO([("data", 8)], rx_fifo_depth)) | ||
# Generate TX IRQ when tx_fifo becomes non-full | ||
tx_irq = ~tx_fifo.sink.ack | ||
self.submodules += tx_fifo, rx_fifo | ||
# TX | ||
tx_fifo = FIFO([("data", 8)], tx_fifo_depth, source_cd=phy_cd) | ||
self.submodules += tx_fifo | ||
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tx_irqs = { | ||
"empty": tx_fifo.source.stb, | ||
"non-full": ~tx_fifo.sink.ack | ||
} | ||
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self.comb += [ | ||
tx_fifo.sink.stb.eq(self._rxtx.re), | ||
tx_fifo.sink.data.eq(self._rxtx.r), | ||
self._txfull.status.eq(~tx_fifo.sink.ack), | ||
Record.connect(tx_fifo.source, phy.sink), | ||
self.ev.tx.trigger.eq(tx_irq), | ||
self.ev.tx.trigger.eq(tx_irqs[tx_irq_condition]) | ||
] | ||
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# RX | ||
rx_fifo = FIFO([("data", 8)], rx_fifo_depth, sink_cd=phy_cd) | ||
self.submodules += rx_fifo | ||
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rx_irqs = { | ||
"non-empty": ~rx_fifo.source.stb, | ||
"full": rx_fifo.sink.ack | ||
} | ||
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self.comb += [ | ||
Record.connect(phy.source, rx_fifo.sink), | ||
self._rxempty.status.eq(~rx_fifo.source.stb), | ||
self._rxtx.w.eq(rx_fifo.source.data), | ||
rx_fifo.source.ack.eq(self.ev.rx.clear), | ||
# Generate RX IRQ when rx_fifo becomes non-empty | ||
self.ev.rx.trigger.eq(~rx_fifo.source.stb), | ||
self.ev.rx.trigger.eq(rx_irqs[rx_irq_condition]) | ||
] |
Does this make such a large difference that it needs a parameter?