Skip to content

Commit

Permalink
misoclib/com/uart: cleanup and add irq condition parameters
Browse files Browse the repository at this point in the history
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
enjoy-digital committed Jul 24, 2015
1 parent b1ea334 commit d73d750
Showing 1 changed file with 26 additions and 19 deletions.
45 changes: 26 additions & 19 deletions misoclib/com/uart/__init__.py
Original file line number Diff line number Diff line change
@@ -2,13 +2,13 @@
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.genlib.record import Record
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
from migen.actorlib.fifo import FIFO


class UART(Module, AutoCSR):
def __init__(self, phy,
tx_fifo_depth=16,
rx_fifo_depth=16,
tx_fifo_depth=16, tx_irq_condition="empty",
rx_fifo_depth=16, rx_irq_condition="non-empty",

This comment has been minimized.

Copy link
@sbourdeauducq

sbourdeauducq Jul 24, 2015

Member

Does this make such a large difference that it needs a parameter?

This comment has been minimized.

Copy link
@enjoy-digital

enjoy-digital Jul 24, 2015

Author Contributor

the tx_irq_condition was not the same between synchronous ("empty") and asynchronous ("non-full") and the choice was not explained.
Adding these parameters allow all possible behaviours and ensure that the default conditions are the same for both cases.

This comment has been minimized.

Copy link
@sbourdeauducq

sbourdeauducq Jul 24, 2015

Member

Yes, but do we need all possible behaviours?

This comment has been minimized.

Copy link
@enjoy-digital

enjoy-digital Jul 24, 2015

Author Contributor

I created an issue for that: #16
I'll do the evaluation (don't have time to do it now) and I'll try remove these parameters if a solution is clearly better than the others.

phy_cd="sys"):
self._rxtx = CSR(8)
self._txfull = CSRStatus()
@@ -21,30 +21,37 @@ def __init__(self, phy,

# # #

if phy_cd == "sys":
tx_fifo = SyncFIFO([("data", 8)], tx_fifo_depth)
rx_fifo = SyncFIFO([("data", 8)], rx_fifo_depth)
# Generate TX IRQ when tx_fifo becomes empty
tx_irq = tx_fifo.source.stb
else:
tx_fifo = ClockDomainsRenamer({"write": "sys", "read": phy_cd})(
AsyncFIFO([("data", 8)], tx_fifo_depth))
rx_fifo = ClockDomainsRenamer({"write": phy_cd, "read": "sys"})(
AsyncFIFO([("data", 8)], rx_fifo_depth))
# Generate TX IRQ when tx_fifo becomes non-full
tx_irq = ~tx_fifo.sink.ack
self.submodules += tx_fifo, rx_fifo
# TX
tx_fifo = FIFO([("data", 8)], tx_fifo_depth, source_cd=phy_cd)
self.submodules += tx_fifo

tx_irqs = {
"empty": tx_fifo.source.stb,
"non-full": ~tx_fifo.sink.ack
}

self.comb += [
tx_fifo.sink.stb.eq(self._rxtx.re),
tx_fifo.sink.data.eq(self._rxtx.r),
self._txfull.status.eq(~tx_fifo.sink.ack),
Record.connect(tx_fifo.source, phy.sink),
self.ev.tx.trigger.eq(tx_irq),
self.ev.tx.trigger.eq(tx_irqs[tx_irq_condition])
]


# RX
rx_fifo = FIFO([("data", 8)], rx_fifo_depth, sink_cd=phy_cd)
self.submodules += rx_fifo

rx_irqs = {
"non-empty": ~rx_fifo.source.stb,
"full": rx_fifo.sink.ack
}

self.comb += [
Record.connect(phy.source, rx_fifo.sink),
self._rxempty.status.eq(~rx_fifo.source.stb),
self._rxtx.w.eq(rx_fifo.source.data),
rx_fifo.source.ack.eq(self.ev.rx.clear),
# Generate RX IRQ when rx_fifo becomes non-empty
self.ev.rx.trigger.eq(~rx_fifo.source.stb),
self.ev.rx.trigger.eq(rx_irqs[rx_irq_condition])
]

0 comments on commit d73d750

Please sign in to comment.