Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/migen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 493f424ebd63
Choose a base ref
...
head repository: m-labs/migen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: d0a19c4be85c
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 24, 2015

  1. migen/fhdl/tools: fix rename_clock_domain when new == old

    Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
    enjoy-digital committed Jul 24, 2015
    Copy the full SHA
    1f1ff5a View commit details
  2. migen/actorlib/fifo: add FIFO wrapper function

    Allow automatic instantiation of the correct fifo (SyncFIFO or AsyncFIFO) according to the clock domains passed in argument.
    enjoy-digital committed Jul 24, 2015
    2
    Copy the full SHA
    d0a19c4 View commit details
Showing with 19 additions and 6 deletions.
  1. +12 −0 migen/actorlib/fifo.py
  2. +7 −6 migen/fhdl/tools.py
12 changes: 12 additions & 0 deletions migen/actorlib/fifo.py
Original file line number Diff line number Diff line change
@@ -55,3 +55,15 @@ def __init__(self, layout, depth, buffered=False):
class AsyncFIFO(_FIFOActor):
def __init__(self, layout, depth):
_FIFOActor.__init__(self, fifo.AsyncFIFO, layout, depth)


def FIFO(layout, depth, buffered=False,
sink_cd="sys", source_cd="sys"):
if sink_cd != source_cd:
if buffered:
ValueError("AsyncFIFO does not support buffered mode")
fifo = AsyncFIFO(layout, depth)
return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
else:
fifo = SyncFIFO(layout, depth, buffered)
return ClockDomainsRenamer(sink_cd)(fifo)
13 changes: 7 additions & 6 deletions migen/fhdl/tools.py
Original file line number Diff line number Diff line change
@@ -256,12 +256,13 @@ def rename_clock_domain_expr(f, old, new):

def rename_clock_domain(f, old, new):
rename_clock_domain_expr(f, old, new)
if old in f.sync:
if new in f.sync:
f.sync[new].extend(f.sync[old])
else:
f.sync[new] = f.sync[old]
del f.sync[old]
if new != old:
if old in f.sync:
if new in f.sync:
f.sync[new].extend(f.sync[old])
else:
f.sync[new] = f.sync[old]
del f.sync[old]
for special in f.specials:
special.rename_clock_domain(old, new)
try: