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misoclib/com/uart: replace revered Migen FIFO function with specific …
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…_get_uart_fifo function for our use case.
enjoy-digital committed Jul 24, 2015
1 parent 0a115f6 commit b75b93d
Showing 1 changed file with 11 additions and 3 deletions.
14 changes: 11 additions & 3 deletions misoclib/com/uart/__init__.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,15 @@
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.genlib.record import Record
from migen.actorlib.fifo import FIFO
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO


def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
if sink_cd != source_cd:
fifo = AsyncFIFO([("data", 8)], depth)
return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
else:
return SyncFIFO([("data", 8)], depth)


class UART(Module, AutoCSR):
@@ -22,7 +30,7 @@ def __init__(self, phy,
# # #

# TX
tx_fifo = FIFO([("data", 8)], tx_fifo_depth, source_cd=phy_cd)
tx_fifo = _get_uart_fifo(tx_fifo_depth, source_cd=phy_cd)
self.submodules += tx_fifo

tx_irqs = {
@@ -40,7 +48,7 @@ def __init__(self, phy,


# RX
rx_fifo = FIFO([("data", 8)], rx_fifo_depth, sink_cd=phy_cd)
rx_fifo = _get_uart_fifo(rx_fifo_depth, sink_cd=phy_cd)
self.submodules += rx_fifo

rx_irqs = {

1 comment on commit b75b93d

@sbourdeauducq
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Thanks

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