Skip to content

Commit f32f9be

Browse files
committedJul 27, 2015
resetless -> reset_less
·
0.9.20.1
1 parent cc6877d commit f32f9be

File tree

2 files changed

+4
-4
lines changed

2 files changed

+4
-4
lines changed
 

‎migen/fhdl/structure.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -327,14 +327,14 @@ class ResetSignal(Value):
327327
----------
328328
cd : str
329329
Clock domain to obtain a reset signal for. Defaults to `"sys"`.
330-
allow_resetless : bool
330+
allow_reset_less : bool
331331
If the clock domain is resetless, return 0 instead of reporting an
332332
error.
333333
"""
334-
def __init__(self, cd="sys", allow_resetless=False):
334+
def __init__(self, cd="sys", allow_reset_less=False):
335335
Value.__init__(self)
336336
self.cd = cd
337-
self.allow_resetless = allow_resetless
337+
self.allow_reset_less = allow_reset_less
338338

339339
# statements
340340

‎migen/fhdl/tools.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@ def visit_ClockSignal(self, node):
193193
def visit_ResetSignal(self, node):
194194
rst = self.clock_domains[node.cd].rst
195195
if rst is None:
196-
if node.allow_resetless:
196+
if node.allow_reset_less:
197197
return 0
198198
else:
199199
raise ValueError("Attempted to get reset signal of resetless"

0 commit comments

Comments
 (0)
Please sign in to comment.