Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/artiq
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 20f5f8217d9c
Choose a base ref
...
head repository: m-labs/artiq
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: ece52062f21a
Choose a head ref

Commits on May 25, 2015

  1. Copy the full SHA
    36cda96 View commit details

Commits on May 27, 2015

  1. Copy the full SHA
    4bf7875 View commit details
  2. Copy the full SHA
    c32133b View commit details
  3. Copy the full SHA
    0b05b54 View commit details
  4. setup/conda: update frontends

    fallen committed May 27, 2015
    Copy the full SHA
    4da377e View commit details

Commits on May 28, 2015

  1. Copy the full SHA
    737f6d4 View commit details
  2. Copy the full SHA
    4a7c695 View commit details
  3. Copy the full SHA
    e752e57 View commit details
  4. Copy the full SHA
    b0f8141 View commit details
  5. scheduler: simplify priority policy

    Remove overdueness. User must submit calibration experiments with higher priority values for them to take precedence.
    sbourdeauducq committed May 28, 2015
    Copy the full SHA
    aa242f7 View commit details

Commits on May 29, 2015

  1. Copy the full SHA
    575dfad View commit details
  2. Copy the full SHA
    ed95038 View commit details
  3. Copy the full SHA
    6ff2e1a View commit details
  4. Copy the full SHA
    048782e View commit details
  5. Copy the full SHA
    7ec0bc0 View commit details
  6. manual: after artiq is installed, frontends can be used without path …

    …prefix
    
    except non-python frontends like artiq_flash.sh
    fallen committed May 29, 2015
    Copy the full SHA
    d5fb50b View commit details
  7. Copy the full SHA
    a84f76b View commit details

Commits on Jun 2, 2015

  1. soc: rtio monitor

    sbourdeauducq committed Jun 2, 2015
    Copy the full SHA
    b81151e View commit details
  2. Copy the full SHA
    59b3394 View commit details
  3. Copy the full SHA
    140239f View commit details

Commits on Jun 3, 2015

  1. 7
    Copy the full SHA
    c7953da View commit details
  2. Copy the full SHA
    e5f16b2 View commit details
  3. Copy the full SHA
    a2ae5e4 View commit details
  4. 2
    Copy the full SHA
    21d88d8 View commit details
  5. Copy the full SHA
    b8bdce5 View commit details
  6. 4
    Copy the full SHA
    b27254b View commit details
  7. Copy the full SHA
    0bf3b7a View commit details

Commits on Jun 4, 2015

  1. Copy the full SHA
    448ba04 View commit details
  2. style fixes

    sbourdeauducq committed Jun 4, 2015
    Copy the full SHA
    82a2bea View commit details
  3. Copy the full SHA
    d730066 View commit details
  4. Copy the full SHA
    78f9268 View commit details
  5. Copy the full SHA
    60bdf74 View commit details
  6. Copy the full SHA
    50a6da9 View commit details
  7. Copy the full SHA
    c843c35 View commit details
  8. worker: wait for process termination

    This prevents stray SIGCHLDs from crashing the program e.g. if the asyncio event loop is closed before the process actually terminates.
    sbourdeauducq committed Jun 4, 2015
    Copy the full SHA
    a6a4765 View commit details

Commits on Jun 5, 2015

  1. Copy the full SHA
    9f90795 View commit details
  2. Copy the full SHA
    14cf244 View commit details
  3. Copy the full SHA
    37c7ea3 View commit details
  4. style

    sbourdeauducq committed Jun 5, 2015
    Copy the full SHA
    26e737f View commit details
  5. fix doc build

    sbourdeauducq committed Jun 5, 2015
    Copy the full SHA
    398940f View commit details
  6. 20
    Copy the full SHA
    c251601 View commit details

Commits on Jun 8, 2015

  1. pxi6733: cleanup

    fallen committed Jun 8, 2015
    3
    Copy the full SHA
    d66117e View commit details
  2. pxi6733: fix type issue

    fallen committed Jun 8, 2015
    Copy the full SHA
    6c094b5 View commit details

Commits on Jun 9, 2015

  1. Copy the full SHA
    b2af0f6 View commit details
  2. Copy the full SHA
    276a178 View commit details
  3. Copy the full SHA
    92999d0 View commit details

Commits on Jun 11, 2015

  1. Copy the full SHA
    f84c51f View commit details

Commits on Jun 12, 2015

  1. Copy the full SHA
    86fbe38 View commit details
  2. Copy the full SHA
    2ed81f7 View commit details

Commits on Jun 14, 2015

  1. Copy the full SHA
    2311642 View commit details
Showing with 6,509 additions and 3,285 deletions.
  1. +12 −12 .travis.yml
  2. +3 −2 .travis/get-anaconda.sh
  3. +8 −7 .travis/get-xilinx.sh
  4. +5 −6 artiq/__init__.py
  5. +28 −3 artiq/compiler/builtins.py
  6. +19 −5 artiq/compiler/ir.py
  7. +1 −1 artiq/compiler/module.py
  8. +116 −47 artiq/compiler/transforms/artiq_ir_generator.py
  9. +56 −35 artiq/compiler/transforms/inferencer.py
  10. +102 −30 artiq/compiler/transforms/llvm_ir_generator.py
  11. +3 −1 artiq/compiler/types.py
  12. +5 −12 artiq/compiler/validators/escape.py
  13. +3 −15 artiq/coredevice/comm_dummy.py
  14. +53 −5 artiq/coredevice/comm_generic.py
  15. +5 −5 artiq/coredevice/comm_serial.py
  16. +4 −5 artiq/coredevice/comm_tcp.py
  17. +13 −20 artiq/coredevice/core.py
  18. +55 −26 artiq/coredevice/dds.py
  19. +5 −4 artiq/coredevice/runtime.py
  20. +154 −83 artiq/coredevice/ttl.py
  21. +6 −20 artiq/devices/lda/driver.py
  22. +87 −135 artiq/devices/novatech409b/driver.py
  23. +21 −29 artiq/devices/pdq2/mediator.py
  24. +95 −27 artiq/devices/pxi6733/driver.py
  25. +177 −0 artiq/devices/pxi6733/mediator.py
  26. +75 −73 artiq/devices/thorlabs_tcube/driver.py
  27. +23 −13 artiq/frontend/artiq_client.py
  28. +4 −5 artiq/frontend/artiq_compile.py
  29. +72 −0 artiq/frontend/artiq_coreconfig.py
  30. +25 −4 artiq/frontend/artiq_flash.sh
  31. +44 −11 artiq/frontend/artiq_gui.py
  32. +31 −19 artiq/frontend/artiq_master.py
  33. +4 −7 artiq/frontend/artiq_mkfs.py
  34. +5 −2 artiq/frontend/artiq_rpctool.py
  35. +30 −51 artiq/frontend/artiq_run.py
  36. +9 −3 artiq/frontend/lda_controller.py
  37. +11 −2 artiq/frontend/novatech409b_controller.py
  38. +12 −2 artiq/frontend/pdq2_controller.py
  39. +14 −9 artiq/frontend/pxi6733_controller.py
  40. +12 −2 artiq/frontend/thorlabs_tcube_controller.py
  41. +23 −20 artiq/gateware/{ad9858.py → ad9xxx.py}
  42. +3 −12 artiq/gateware/amp/kernel_cpu.py
  43. +14 −2 artiq/gateware/nist_qc1.py
  44. +78 −0 artiq/gateware/nist_qc2.py
  45. +1 −0 artiq/gateware/rtio/__init__.py
  46. +26 −8 artiq/gateware/rtio/core.py
  47. +68 −0 artiq/gateware/rtio/moninj.py
  48. +60 −0 artiq/gateware/rtio/phy/dds.py
  49. +62 −4 artiq/gateware/rtio/phy/ttl_simple.py
  50. +3 −2 artiq/gateware/soc.py
  51. +130 −0 artiq/gui/displays.py
  52. +157 −21 artiq/gui/explorer.py
  53. BIN artiq/gui/icon.png
  54. +51 −1 artiq/gui/log.py
  55. +300 −0 artiq/gui/moninj.py
  56. +29 −5 artiq/gui/parameters.py
  57. +109 −0 artiq/gui/results.py
  58. +137 −0 artiq/gui/scan.py
  59. +8 −8 artiq/gui/schedule.py
  60. +93 −16 artiq/gui/tools.py
  61. +12 −0 artiq/language/__init__.py
  62. +44 −45 artiq/language/core.py
  63. +0 −130 artiq/language/db.py
  64. +298 −0 artiq/language/environment.py
  65. +0 −40 artiq/language/experiment.py
  66. +114 −0 artiq/language/scan.py
  67. +7 −253 artiq/language/units.py
  68. +53 −22 artiq/master/repository.py
  69. +0 −103 artiq/master/results.py
  70. +70 −63 artiq/master/scheduler.py
  71. +50 −27 artiq/master/worker.py
  72. +99 −65 artiq/master/worker_db.py
  73. +79 −25 artiq/master/worker_impl.py
  74. +1 −17 artiq/protocols/file_db.py
  75. +45 −0 artiq/protocols/fire_and_forget.py
  76. +20 −7 artiq/protocols/pc_rpc.py
  77. +0 −9 artiq/protocols/pyon.py
  78. +26 −36 artiq/protocols/sync_struct.py
  79. +2 −2 artiq/py2llvm_old/__init__.py
  80. +11 −11 artiq/py2llvm_old/ast_body.py
  81. +1 −1 artiq/py2llvm_old/base_types.py
  82. +1 −1 artiq/py2llvm_old/fractions.py
  83. +1 −1 artiq/py2llvm_old/lists.py
  84. +9 −9 artiq/py2llvm_old/module.py
  85. +1 −1 artiq/py2llvm_old/tools.py
  86. +1 −1 artiq/py2llvm_old/values.py
  87. +19 −19 artiq/sim/devices.py
  88. +10 −8 artiq/sim/time.py
  89. +4 −4 artiq/test/coefficients.py
  90. +276 −0 artiq/test/coredevice.py
  91. +220 −0 artiq/test/coredevice_vs_host.py
  92. +0 −371 artiq/test/full_stack.py
  93. +58 −0 artiq/test/hardware_testbench.py
  94. +7 −13 artiq/test/lda.py
  95. +31 −0 artiq/test/novatech409b.py
  96. +21 −4 artiq/test/pc_rpc.py
  97. +1 −1 artiq/test/py2llvm.py
  98. +169 −0 artiq/test/scheduler.py
  99. +82 −0 artiq/test/sync_struct.py
  100. +4 −10 artiq/test/thorlabs_tcube.py
  101. +7 −13 artiq/test/transforms.py
  102. +22 −12 artiq/test/worker.py
  103. +53 −14 artiq/tools.py
  104. +4 −3 artiq/transforms/interleave.py
  105. +9 −9 artiq/transforms/lower_time.py
  106. +0 −190 artiq/transforms/lower_units.py
  107. +16 −31 artiq/transforms/quantize_time.py
  108. +5 −18 artiq/transforms/tools.py
  109. +25 −30 artiq/wavesynth/coefficients.py
  110. +4 −0 artiq/wavesynth/compute_samples.py
  111. +0 −18 benchmarks/all.py
  112. +0 −28 benchmarks/ddb.pyon
  113. +0 −1 benchmarks/pdb.pyon
  114. +0 −26 benchmarks/pulse_rate.py
  115. +0 −32 benchmarks/rpc_timing.py
  116. +0 −29 benchmarks/rtio_skew.py
  117. +15 −7 conda/artiq/build.sh
  118. +6 −3 conda/artiq/meta.yaml
  119. +0 −15 conda/cairo/build.sh
  120. +0 −25 conda/cairo/meta.yaml
  121. +0 −29 conda/cairoplot3-artiq/meta.yaml
  122. +5 −0 conda/flterm/build.sh
  123. +12 −0 conda/flterm/meta.yaml
  124. +0 −28 conda/gbulb-artiq/meta.yaml
  125. +1 −0 conda/llvmdev-or1k/meta.yaml
  126. +2 −0 conda/llvmlite-or1k/bld.bat
  127. +2 −0 conda/llvmlite-or1k/build.sh
  128. +3 −3 conda/llvmlite-or1k/meta.yaml
  129. +0 −1 conda/pycairo/bld.bat
  130. +0 −3 conda/pycairo/build.sh
  131. +0 −29 conda/pycairo/meta.yaml
  132. +0 −6 conda/pygobject/build.sh
  133. +0 −30 conda/pygobject/meta.yaml
  134. +3 −4 conda/pyqtgraph/meta.yaml
  135. +1 −1 doc/manual/conf.py
  136. +14 −0 doc/manual/core_device_flash_storage.rst
  137. +3 −0 doc/manual/core_drivers_reference.rst
  138. +3 −3 doc/manual/core_language_reference.rst
  139. +3 −1 doc/manual/default_network_ports.rst
  140. +2 −2 doc/manual/developing_a_ndsp.rst
  141. +24 −14 doc/manual/faq.rst
  142. +20 −14 doc/manual/fpga_board_ports.rst
  143. +23 −21 doc/manual/getting_started.rst
  144. +1 −0 doc/manual/index.rst
  145. +173 −37 doc/manual/installing.rst
  146. +42 −0 doc/manual/ndsp_reference.rst
  147. +8 −0 doc/manual/protocols_reference.rst
  148. +58 −0 doc/manual/utilities.rst
  149. +8 −6 doc/slides/artiq_overview.tex
  150. +8 −6 doc/slides/taaccs.tex
  151. +15 −10 examples/master/ddb.pyon
  152. +21 −0 examples/master/repository/arguments_demo.py
  153. +11 −11 examples/master/repository/dds_test.py
  154. +13 −17 examples/master/repository/flopping_f_simulation.py
  155. +4 −4 examples/master/repository/handover.py
  156. +3 −3 examples/master/repository/mandelbrot.py
  157. +16 −22 examples/master/repository/photon_histogram.py
  158. +14 −15 examples/master/repository/transport.py
  159. +12 −12 examples/sim/al_spectroscopy.py
  160. +12 −17 examples/sim/simple_simulation.py
  161. +15 −0 lit-test/compiler/inferencer/unify.py
  162. +13 −0 misc/llvmlite-build-as-debug-on-windows.patch
  163. +65 −0 misc/llvmlite-rename.patch
  164. +28 −0 misc/pyqtgraph-do-not-close-nonclosable-docks.patch
  165. +9 −0 setup.py
  166. +1 −1 soc/runtime/Makefile
  167. +2 −2 soc/runtime/bridge.c
  168. +104 −22 soc/runtime/dds.c
  169. +31 −4 soc/runtime/dds.h
  170. +230 −113 soc/runtime/flash_storage.c
  171. +2 −1 soc/runtime/flash_storage.h
  172. +1 −0 soc/runtime/gen_service_table.py
  173. +1 −1 soc/runtime/ksupport.c
  174. +2 −2 soc/runtime/liblwip/lwipopts.h
  175. +1 −1 soc/runtime/lwip
  176. +0 −15 soc/runtime/mailbox.c
  177. +23 −22 soc/runtime/main.c
  178. +156 −0 soc/runtime/moninj.c
  179. +6 −0 soc/runtime/moninj.h
  180. +0 −1 soc/runtime/rtio.c
  181. +3 −2 soc/runtime/services.c
  182. +95 −16 soc/runtime/session.c
  183. +262 −18 soc/runtime/test_mode.c
  184. +8 −0 soc/runtime/ttl.c
  185. +1 −0 soc/runtime/ttl.h
  186. +91 −38 soc/targets/artiq_kc705.py
  187. +47 −37 soc/targets/artiq_pipistrello.py
24 changes: 12 additions & 12 deletions .travis.yml
Original file line number Diff line number Diff line change
@@ -7,37 +7,37 @@ branches:
sudo: false
env:
global:
- MSCDIR=$TRAVIS_BUILD_DIR/misoc
- PATH=$HOME/miniconda/bin:/usr/local/llvm-or1k/bin:$PATH
- BUILD_SOC=1
- secure: "DUk/Ihg8KbbzEgPF0qrHqlxU8e8eET9i/BtzNvFddIGX4HP/P2qz0nk3cVkmjuWhqJXSbC22RdKME9qqPzw6fJwJ6dpJ3OR6dDmSd7rewavq+niwxu52PVa+yK8mL4yf1terM7QQ5tIRf+yUL9qGKrZ2xyvEuRit6d4cFep43Ws="
before_install:
- mkdir -p $HOME/.mlabs
- if [ $TRAVIS_PULL_REQUEST != false ]; then BUILD_SOC=0; fi
- . ./.travis/get-toolchain.sh
- if [ $BUILD_SOC -ne 0 ]; then ./.travis/get-xilinx.sh; fi
- ./.travis/get-anaconda.sh
- . ./.travis/get-toolchain.sh
- . ./.travis/get-anaconda.sh
- source $HOME/miniconda/bin/activate py34
- conda install pip coverage binstar migen cython
- conda install -q pip coverage binstar migen cython
- pip install coveralls
install:
- conda build conda/artiq
- conda install $HOME/miniconda/conda-bld/linux-64/artiq-*.tar.bz2
- conda install -q artiq --use-local
script:
- coverage run --source=artiq setup.py test
- make -C doc/manual html
after_success:
- binstar login --hostname $(hostname) --username $binstar_login --password $binstar_password
- binstar upload --user $binstar_login --channel dev --force $HOME/miniconda/conda-bld/linux-64/artiq-*.tar.bz2
- binstar -q login --hostname $(hostname) --username $binstar_login --password $binstar_password
- binstar -q upload --user $binstar_login --channel dev --force $HOME/miniconda/conda-bld/linux-64/artiq-*.tar.bz2
- binstar -q logout
- coveralls
notifications:
email: false
email:
recipients:
- rjordens@nist.gov
on_success: always
on_failure: never
irc:
channels:
- chat.freenode.net#m-labs
template:
- "%{repository}#%{build_number} (%{branch} - %{commit} : %{author}): %{message}"
- "Build details : %{build_url}"
webhooks:
urls:
- https://webhooks.gitter.im/e/d26782523952bfa53814
5 changes: 3 additions & 2 deletions .travis/get-anaconda.sh
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
#!/bin/sh

wget http://repo.continuum.io/miniconda/Miniconda3-3.7.3-Linux-x86_64.sh -O miniconda.sh
export PATH=$HOME/miniconda/bin:$PATH
wget http://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh -O miniconda.sh
bash miniconda.sh -b -p $HOME/miniconda
hash -r
conda config --set always_yes yes --set changeps1 no
@@ -9,4 +10,4 @@ conda info -a
conda install conda-build jinja2
conda create -q -n py34 python=$TRAVIS_PYTHON_VERSION
conda config --add channels fallen
conda config --add channels https://conda.binstar.org/fallen/channel/dev
conda config --add channels https://conda.anaconda.org/fallen/channel/dev
15 changes: 8 additions & 7 deletions .travis/get-xilinx.sh
Original file line number Diff line number Diff line change
@@ -24,12 +24,13 @@ echo "$secret" | gpg --passphrase-fd 0 Xilinx.lic.gpg
mkdir -p ~/.Xilinx
mv Xilinx.lic ~/.Xilinx/Xilinx.lic

# Tell mibuild where Vivado is installed
echo "MISOC_EXTRA_VIVADO_CMDLINE=\"-Ob vivado_path $HOME/Xilinx/Vivado\"" >> $HOME/.mlabs/build_settings.sh
echo "MISOC_EXTRA_ISE_CMDLINE=\"-Ob ise_path $HOME/opt/Xilinx/\"" >> $HOME/.mlabs/build_settings.sh

# Lie to Vivado by hooking the ioctl used to retrieve mac address for license verification
git clone https://github.com/fallen/impersonate_macaddress
make -C impersonate_macaddress
echo "export MACADDR=$macaddress" >> $HOME/.mlabs/build_settings.sh
echo "export LD_PRELOAD=$PWD/impersonate_macaddress/impersonate_macaddress.so" >> $HOME/.mlabs/build_settings.sh
# Tell mibuild where Xilinx toolchains are installed
# and feed it the mac address corresponding to the license
cat > $HOME/.mlabs/build_settings.sh << EOF
MISOC_EXTRA_VIVADO_CMDLINE="-Ob vivado_path $HOME/Xilinx/Vivado"
MISOC_EXTRA_ISE_CMDLINE="-Ob ise_path $HOME/opt/Xilinx/"
export MACADDR=$macaddress
export LD_PRELOAD=$PWD/impersonate_macaddress/impersonate_macaddress.so
EOF
11 changes: 5 additions & 6 deletions artiq/__init__.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
from artiq.language.core import *
from artiq.language.experiment import Experiment
from artiq.language.db import *
from artiq.language.units import check_unit
from artiq.language.units import ps, ns, us, ms, s
from artiq.language.units import Hz, kHz, MHz, GHz
from artiq import language
from artiq.language import *

__all__ = []
__all__.extend(language.__all__)
31 changes: 28 additions & 3 deletions artiq/compiler/builtins.py
Original file line number Diff line number Diff line change
@@ -72,6 +72,26 @@ def __init__(self, elt=None):
])

class TException(types.TMono):
# All exceptions share the same internal layout:
# * Pointer to the unique global with the name of the exception (str)
# (which also serves as the EHABI type_info).
# * File, line and column where it was raised (str, int, int).
# * Message, which can contain substitutions {0}, {1} and {2} (str).
# * Three 64-bit integers, parameterizing the message (int(width=64)).


# Keep this in sync with the function ARTIQIRGenerator.alloc_exn.
attributes = OrderedDict([
("__name__", TStr()),
("__file__", TStr()),
("__line__", TInt(types.TValue(32))),
("__col__", TInt(types.TValue(32))),
("__message__", TStr()),
("__param0__", TInt(types.TValue(64))),
("__param1__", TInt(types.TValue(64))),
("__param2__", TInt(types.TValue(64))),
])

def __init__(self, name="Exception"):
super().__init__(name)

@@ -170,8 +190,12 @@ def is_range(typ, elt=None):
else:
return types.is_mono(typ, "range")

def is_exception(typ):
return isinstance(typ.find(), TException)
def is_exception(typ, name=None):
if name is None:
return isinstance(typ.find(), TException)
else:
return isinstance(typ.find(), TException) and \
typ.name == name

def is_iterable(typ):
typ = typ.find()
@@ -189,4 +213,5 @@ def is_collection(typ):

def is_allocated(typ):
return typ.fold(False, lambda accum, typ:
is_list(typ) or is_str(typ) or types.is_function(typ))
is_list(typ) or is_str(typ) or types.is_function(typ) or
is_exception(typ))
24 changes: 19 additions & 5 deletions artiq/compiler/ir.py
Original file line number Diff line number Diff line change
@@ -29,6 +29,13 @@ def __init__(self, inner):
def is_option(typ):
return isinstance(typ, TOption)

class TExceptionTypeInfo(types.TMono):
def __init__(self):
super().__init__("exntypeinfo")

def is_exn_typeinfo(typ):
return isinstance(typ, TExceptionTypeInfo)

class Value:
"""
An SSA value that keeps track of its uses.
@@ -620,7 +627,7 @@ def __init__(self, obj, attr, value, name=""):
assert value.type == obj.type.elts[attr]
else:
assert value.type == obj.type.attributes[attr]
super().__init__([obj, value], typ, name)
super().__init__([obj, value], builtins.TNone(), name)
self.attr = attr

def opcode(self):
@@ -1004,7 +1011,7 @@ def __init__(self, func, args, normal, exn, name=""):
def opcode(self):
return "invoke"

def function(self):
def target_function(self):
return self.operands[0]

def arguments(self):
@@ -1038,17 +1045,24 @@ def __init__(self, name=""):
super().__init__([], builtins.TException(), name)
self.types = []

def clauses(self):
return zip(self.operands, self.types)

def add_clause(self, target, typ):
assert isinstance(target, BasicBlock)
assert builtins.is_exception(typ)
assert typ is None or builtins.is_exception(typ)
self.operands.append(target)
self.types.append(typ.find())
self.types.append(typ.find() if typ is not None else None)
target.uses.add(self)

def opcode(self):
return "landingpad"

def _operands_as_string(self):
table = []
for typ, target in zip(self.types, self.operands):
table.append("{} => {}".format(types.TypePrinter().name(typ), target.as_operand()))
if typ is None:
table.append("... => {}".format(target.as_operand()))
else:
table.append("{} => {}".format(types.TypePrinter().name(typ), target.as_operand()))
return "[{}]".format(", ".join(table))
2 changes: 1 addition & 1 deletion artiq/compiler/module.py
Original file line number Diff line number Diff line change
@@ -33,7 +33,7 @@ def __init__(self, source_buffer, engine=None):
escape_validator.visit(self.typedtree)
self.artiq_ir = artiq_ir_generator.visit(self.typedtree)
dead_code_eliminator.process(self.artiq_ir)
local_access_validator.process(self.artiq_ir)
# local_access_validator.process(self.artiq_ir)
self.llvm_ir = llvm_ir_generator.process(self.artiq_ir)

@classmethod
Loading