misoclib/com/uart: remove irq condition parameters and use "non-full" for tx irq, "non-empty" for rx irq.

enjoy-digital · enjoy-digital · commit 4c601cc1bd5b · 2015-07-25T00:21:59.000+02:00
An optimal solution for both sync and async mode is not easy to implement, it would requires moving CDC out of UART module and handling in the PHY with AsyncFIFO or minimal depth.
For now use the solution that works for both cases. We'll try to optimize that if we have performance issues.
diff --git a/misoclib/com/uart/__init__.py b/misoclib/com/uart/__init__.py
@@ -15,8 +15,8 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
 
 class UART(Module, AutoCSR):
     def __init__(self, phy,
-                 tx_fifo_depth=16, tx_irq_condition="empty",
-                 rx_fifo_depth=16, rx_irq_condition="non-empty",
+                 tx_fifo_depth=16,
+                 rx_fifo_depth=16,
                  phy_cd="sys"):
         self._rxtx = CSR(8)
         self._txfull = CSRStatus()
@@ -33,33 +33,26 @@ def __init__(self, phy,
         tx_fifo = _get_uart_fifo(tx_fifo_depth, source_cd=phy_cd)
         self.submodules += tx_fifo
 
-        tx_irqs = {
-            "empty": tx_fifo.source.stb,
-            "non-full": ~tx_fifo.sink.ack
-        }
-
         self.comb += [
             tx_fifo.sink.stb.eq(self._rxtx.re),
             tx_fifo.sink.data.eq(self._rxtx.r),
             self._txfull.status.eq(~tx_fifo.sink.ack),
             Record.connect(tx_fifo.source, phy.sink),
-            self.ev.tx.trigger.eq(tx_irqs[tx_irq_condition])
+			# Generate TX IRQ when tx_fifo becomes non-full
+            self.ev.tx.trigger.eq(~tx_fifo.sink.ack)
         ]
 
 
         # RX
         rx_fifo = _get_uart_fifo(rx_fifo_depth, sink_cd=phy_cd)
         self.submodules += rx_fifo
 
-        rx_irqs = {
-            "non-empty": ~rx_fifo.source.stb,
-            "full": rx_fifo.sink.ack
-        }
 
         self.comb += [
             Record.connect(phy.source, rx_fifo.sink),
             self._rxempty.status.eq(~rx_fifo.source.stb),
             self._rxtx.w.eq(rx_fifo.source.data),
             rx_fifo.source.ack.eq(self.ev.rx.clear),
-            self.ev.rx.trigger.eq(rx_irqs[rx_irq_condition])
+            # Generate RX IRQ when tx_fifo becomes non-empty
+            self.ev.rx.trigger.eq(~rx_fifo.source.stb)
         ]
