litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files

enjoy-digital · enjoy-digital · commit 40740d3ddc04 · 2015-07-22T18:09:04.000+02:00
We should eventually try to use python package_data or data_file for that.
diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -69,6 +69,7 @@ def __init__(self, platform, with_uart_bridge=True):
             with_timer=False
         )
         self.submodules.crg = _CRG(platform)
+        platform.misoc_path = "../../../../"
 
         # PCIe endpoint
         self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)
diff --git a/misoclib/com/litepcie/phy/s7pciephy.py b/misoclib/com/litepcie/phy/s7pciephy.py
@@ -151,15 +151,13 @@ def convert_size(command, size):
             convert_size(dcommand[12:15], self.max_request_size),
             convert_size(dcommand[5:8], self.max_payload_size)
         ]
-
-        extcores_path = "extcores"
-        # XXX find a better way to do this?
-        current_path = os.getcwd()
-        current_path = current_path.replace("\\", "/")
-        if "litepcie/example_designs" in current_path:
-            extcores_path = os.path.join("..", "..", "..", "..", extcores_path)
-        platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "common"))
+        if hasattr(platform, "misoc_path"):
+            misoc_path = platform.misoc_path
+        else:
+            misoc_path = "./"
+        litepcie_phy_wrapper_path = os.path.join(misoc_path, "extcores", "litepcie_phy_wrappers")
+        platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "common"))
         if device[:4] == "xc7k":
-            platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "kintex7"))
+            platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "kintex7"))
         elif device[:4] == "xc7a":
-            platform.add_source_dir(os.path.join(extcores_path, "litepcie_phy_wrappers", "xilinx", "7-series", "artix7"))
+            platform.add_source_dir(os.path.join(litepcie_phy_wrapper_path, "xilinx", "7-series", "artix7"))

Original file line number	Diff line number	Diff line change
`@@ -69,6 +69,7 @@ def __init__(self, platform, with_uart_bridge=True):`
`69`	`69`	`with_timer=False`
`70`	`70`	`)`
`71`	`71`	`self.submodules.crg = _CRG(platform)`
	`72`	`+ platform.misoc_path = "../../../../"`
`72`	`73`
`73`	`74`	`# PCIe endpoint`
`74`	`75`	`self.submodules.pcie_phy = S7PCIEPHY(platform, link_width=2)`