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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 2640a57af3e9
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Jul 28, 2015

  1. ttl: remove spurious _mu

    jordens committed Jul 28, 2015
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    e95b66f View commit details
  2. ttl: add timestamp()

    jordens committed Jul 28, 2015
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    5f5227f View commit details
  3. Copy the full SHA
    2640a57 View commit details
Showing with 14 additions and 4 deletions.
  1. +13 −3 artiq/coredevice/ttl.py
  2. +1 −1 artiq/test/coredevice.py
16 changes: 13 additions & 3 deletions artiq/coredevice/ttl.py
Original file line number Diff line number Diff line change
@@ -177,7 +177,7 @@ def gate_falling(self, duration):
self._set_sensitivity(0)

@kernel
def gate_both_mu(self, duration):
def gate_both(self, duration):
"""Register both rising and falling edge events for the specified
duration (in seconds)."""
self._set_sensitivity(3)
@@ -196,13 +196,23 @@ def count(self):

@kernel
def timestamp_mu(self):
"""Poll the RTIO input and returns an event timestamp, according to
the gating.
"""Poll the RTIO input and returns an event timestamp (in machine
units), according to the gating.
If the gate is permanently closed, returns a negative value.
"""
return syscall("ttl_get", self.channel, self.i_previous_timestamp)

@kernel
def timestamp(self):
"""Poll the RTIO input and returns an event timestamp (in seconds),
according to the gating.
If the gate is permanently closed, returns a negative value.
"""
return mu_to_seconds(
syscall("ttl_get", self.channel, self.i_previous_timestamp))


class TTLClockGen:
"""RTIO TTL clock generator driver.
2 changes: 1 addition & 1 deletion artiq/test/coredevice.py
Original file line number Diff line number Diff line change
@@ -120,7 +120,7 @@ def set_count(self, count):
@kernel
def run(self):
self.ttl_inout.output()
delay(1*us)
delay(5*us)
with parallel:
self.ttl_inout.gate_rising(10*us)
with sequential: