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  • 4 commits
  • 8 files changed
  • 1 contributor

Commits on Jul 27, 2015

  1. kc705: crg cleanup

    sbourdeauducq committed Jul 27, 2015
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Showing with 109 additions and 30 deletions.
  1. +1 −1 soc/runtime/Makefile
  2. +10 −0 soc/runtime/clock.c
  3. +1 −0 soc/runtime/clock.h
  4. +2 −4 soc/runtime/main.c
  5. +64 −0 soc/runtime/rtiocrg.c
  6. +8 −0 soc/runtime/rtiocrg.h
  7. +16 −22 soc/runtime/session.c
  8. +7 −3 soc/targets/artiq_kc705.py
2 changes: 1 addition & 1 deletion soc/runtime/Makefile
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
include $(MSCDIR)/software/common.mak

OBJECTS := isr.o flash_storage.o clock.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o moninj.o main.o
OBJECTS := isr.o flash_storage.o clock.o rtiocrg.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o moninj.o main.o
OBJECTS_KSUPPORT := ksupport.o exception_jmp.o exceptions.o mailbox.o bridge.o rtio.o ttl.o dds.o

CFLAGS += -Ilwip/src/include -Iliblwip
10 changes: 10 additions & 0 deletions soc/runtime/clock.c
Original file line number Diff line number Diff line change
@@ -26,6 +26,16 @@ long long int clock_get_ms(void)
return clock_ms;
}

void busywait_us(long long int us)
{
long long int threshold;

timer0_update_value_write(1);
threshold = timer0_value_read() - us*(long long int)identifier_frequency_read()/1000000LL;
while(timer0_value_read() > threshold)
timer0_update_value_write(1);
}

struct watchdog {
int active;
long long int threshold;
1 change: 1 addition & 0 deletions soc/runtime/clock.h
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@

void clock_init(void);
long long int clock_get_ms(void);
void busywait_us(long long us);

#define MAX_WATCHDOGS 16

6 changes: 2 additions & 4 deletions soc/runtime/main.c
Original file line number Diff line number Diff line change
@@ -24,6 +24,7 @@
#include "kloader.h"
#include "flash_storage.h"
#include "clock.h"
#include "rtiocrg.h"
#include "test_mode.h"
#include "kserver.h"
#include "session.h"
@@ -250,13 +251,10 @@ int main(void)
puts("ARTIQ runtime built "__DATE__" "__TIME__"\n");

clock_init();
rtiocrg_init();
puts("Press 't' to enter test mode...");
blink_led();

#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
rtio_crg_pll_reset_write(0);
#endif

if(check_test_mode()) {
puts("Entering test mode.");
test_main();
64 changes: 64 additions & 0 deletions soc/runtime/rtiocrg.c
Original file line number Diff line number Diff line change
@@ -0,0 +1,64 @@
#include <stdio.h>
#include <generated/csr.h>

#include "clock.h"
#include "flash_storage.h"
#include "rtiocrg.h"

void rtiocrg_init(void)
{
char b;
int clk;

#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
rtio_crg_pll_reset_write(0);
#endif
b = 'i';
clk = 0;
fs_read("startup_clock", &b, 1, NULL);
if(b == 'i')
printf("Startup RTIO clock: internal\n");
else if(b == 'e') {
printf("Startup RTIO clock: external\n");
clk = 1;
} else
printf("WARNING: unknown startup_clock entry in flash storage\n");

if(!rtiocrg_switch_clock(clk))
printf("WARNING: startup RTIO clock failed\n");
}

int rtiocrg_check(void)
{
#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
return rtio_crg_pll_locked_read();
#else
return 1;
#endif
}

int rtiocrg_switch_clock(int clk)
{
int current_clk;

current_clk = rtio_crg_clock_sel_read();
if(clk == current_clk) {
#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
busywait_us(150);
if(!rtio_crg_pll_locked_read())
return 0;
#endif
return 1;
}
#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
rtio_crg_pll_reset_write(1);
#endif
rtio_crg_clock_sel_write(clk);
#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
rtio_crg_pll_reset_write(0);
busywait_us(150);
if(!rtio_crg_pll_locked_read())
return 0;
#endif
return 1;
}
8 changes: 8 additions & 0 deletions soc/runtime/rtiocrg.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,8 @@
#ifndef __RTIOCRG_H
#define __RTIOCRG_H

void rtiocrg_init(void);
int rtiocrg_check(void);
int rtiocrg_switch_clock(int clk);

#endif /* __RTIOCRG_H */
38 changes: 16 additions & 22 deletions soc/runtime/session.c
Original file line number Diff line number Diff line change
@@ -12,6 +12,7 @@
#include "kloader.h"
#include "exceptions.h"
#include "flash_storage.h"
#include "rtiocrg.h"
#include "session.h"

#define BUFFER_IN_SIZE (1024*1024)
@@ -128,22 +129,6 @@ static int check_flash_storage_key_len(char *key, unsigned int key_len)
return 1;
}

static void switch_clock(int clk)
{
int current_clk;

current_clk = rtio_crg_clock_sel_read();
if(clk == current_clk)
return;
#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
rtio_crg_pll_reset_write(1);
#endif
rtio_crg_clock_sel_write(clk);
#ifdef CSR_RTIO_CRG_PLL_RESET_ADDR
rtio_crg_pll_reset_write(0);
#endif
}

static int process_input(void)
{
switch(buffer_in[8]) {
@@ -170,8 +155,10 @@ static int process_input(void)
submit_output(9);
break;
}
switch_clock(buffer_in[9]);
buffer_out[8] = REMOTEMSG_TYPE_CLOCK_SWITCH_COMPLETED;
if(rtiocrg_switch_clock(buffer_in[9]))
buffer_out[8] = REMOTEMSG_TYPE_CLOCK_SWITCH_COMPLETED;
else
buffer_out[8] = REMOTEMSG_TYPE_CLOCK_SWITCH_FAILED;
submit_output(9);
break;
case REMOTEMSG_TYPE_LOAD_OBJECT:
@@ -543,10 +530,17 @@ void session_poll(void **data, int *len)
{
int l;

if((user_kernel_state == USER_KERNEL_RUNNING) && watchdog_expired()) {
log("Watchdog expired");
*len = -1;
return;
if(user_kernel_state == USER_KERNEL_RUNNING) {
if(watchdog_expired()) {
log("Watchdog expired");
*len = -1;
return;
}
if(!rtiocrg_check()) {
log("RTIO clock failure");
*len = -1;
return;
}
}

l = get_out_packet_len();
10 changes: 7 additions & 3 deletions soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -49,17 +49,21 @@ def __init__(self, platform, rtio_internal_clk):
i_CLKFBIN=self.cd_rtio.clk,
i_RST=self._pll_reset.storage,

p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0,
o_CLKFBOUT=rtio_clk,
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=rtiox4_clk),

p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=rtiox4_clk),
Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),

AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
MultiReg(pll_locked, self._pll_locked.status)
]

# 62.5MHz when using internal RTIO clock
ext_clkout = platform.request("user_sma_gpio_p")
self.sync.rtio += ext_clkout.eq(~ext_clkout)


class _NIST_QCx(MiniSoC, AMPSoC):
csr_map = {