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Commit 1809a70

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jordensjordens
committedJul 28, 2015
Revert "pipistrello: use 4x serdes for rtio ttl"
This reverts commit 8e92cc9. Broken. Will revisit.
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8.00.1
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Diff for: ‎soc/targets/artiq_pipistrello.py

+32-77
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,6 @@
33
from migen.fhdl.std import *
44
from migen.bank.description import *
55
from migen.bank import wbgen
6-
from migen.genlib.resetsync import AsyncResetSynchronizer
7-
from migen.genlib.cdc import MultiReg
86

97
from misoclib.com import gpio
108
from misoclib.soc import mem_decoder
@@ -13,84 +11,46 @@
1311

1412
from artiq.gateware.soc import AMPSoC
1513
from artiq.gateware import rtio, nist_qc1
16-
from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_spartan6, dds
14+
from artiq.gateware.rtio.phy import ttl_simple, dds
1715

1816

1917
class _RTIOCRG(Module, AutoCSR):
2018
def __init__(self, platform, clk_freq):
2119
self._clock_sel = CSRStorage()
22-
self._pll_reset = CSRStorage(reset=1)
23-
self._pll_locked = CSRStatus()
20+
self.clock_domains.cd_rtio = ClockDomain(reset_less=True)
2421

25-
self.clock_domains.cd_rtio = ClockDomain()
26-
self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
27-
self.clock_domains.cd_rtiox8 = ClockDomain(reset_less=True)
28-
self.rtiox4_stb = Signal()
29-
self.rtiox8_stb = Signal()
30-
31-
rtio_f = 125*1000*1000
32-
f = Fraction(rtio_f, clk_freq)
22+
f = Fraction(125*1000*1000, clk_freq)
3323
rtio_internal_clk = Signal()
34-
rtio_external_clk = Signal()
35-
pmt2 = platform.request("pmt", 2)
36-
dcm_locked = Signal()
37-
rtio_clk = Signal()
38-
pll_locked = Signal()
39-
pll = Signal(3)
40-
pll_fb = Signal()
41-
self.specials += [
42-
Instance("IBUFG", i_I=pmt2, o_O=rtio_external_clk),
43-
Instance("DCM_CLKGEN", p_CLKFXDV_DIVIDE=2,
44-
p_CLKFX_DIVIDE=f.denominator, p_CLKFX_MD_MAX=float(f),
45-
p_CLKFX_MULTIPLY=f.numerator, p_CLKIN_PERIOD=1e9/clk_freq,
46-
p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
47-
i_CLKIN=ClockSignal(), o_CLKFX=rtio_internal_clk,
48-
i_FREEZEDCM=0, i_RST=ResetSignal(), o_LOCKED=dcm_locked),
49-
Instance("BUFGMUX",
50-
i_I0=rtio_internal_clk, i_I1=rtio_external_clk,
51-
i_S=self._clock_sel.storage, o_O=rtio_clk),
52-
Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
53-
p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
54-
p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
55-
i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0,
56-
i_RST=self._pll_reset.storage | ~dcm_locked, i_REL=0,
57-
p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=8,
58-
p_CLKFBOUT_PHASE=0., i_CLKINSEL=1,
59-
i_CLKIN1=rtio_clk, i_CLKIN2=0,
60-
p_CLKIN1_PERIOD=1e9/rtio_f, p_CLKIN2_PERIOD=0.,
61-
i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_locked,
62-
o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
63-
o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
64-
o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
65-
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=1,
66-
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=2,
67-
p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=8),
68-
Instance("BUFPLL", p_DIVIDE=8,
69-
i_PLLIN=pll[0], i_GCLK=self.cd_rtio.clk,
70-
i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox8.clk,
71-
o_SERDESSTROBE=self.rtiox8_stb),
72-
Instance("BUFPLL", p_DIVIDE=4,
73-
i_PLLIN=pll[1], i_GCLK=self.cd_rtio.clk,
74-
i_LOCKED=pll_locked, o_IOCLK=self.cd_rtiox4.clk,
75-
o_SERDESSTROBE=self.rtiox4_stb),
76-
Instance("BUFG", i_I=pll[2], o_O=self.cd_rtio.clk),
77-
AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
78-
MultiReg(pll_locked, self._pll_locked.status),
79-
]
24+
self.specials += Instance("DCM_CLKGEN",
25+
p_CLKFXDV_DIVIDE=2,
26+
p_CLKFX_DIVIDE=f.denominator,
27+
p_CLKFX_MD_MAX=float(f),
28+
p_CLKFX_MULTIPLY=f.numerator,
29+
p_CLKIN_PERIOD=1e9/clk_freq,
30+
p_SPREAD_SPECTRUM="NONE",
31+
p_STARTUP_WAIT="FALSE",
32+
i_CLKIN=ClockSignal(),
33+
o_CLKFX=rtio_internal_clk,
34+
i_FREEZEDCM=0,
35+
i_RST=ResetSignal())
36+
37+
rtio_external_clk = platform.request("pmt", 2)
38+
# ISE infers constraints for the internal clock
39+
# and propagates them through the BUFGMUX. Adding this:
40+
# platform.add_period_constraint(rtio_external_clk, 8.0)
41+
# seems to confuse it
42+
self.specials += Instance("BUFGMUX",
43+
i_I0=rtio_internal_clk,
44+
i_I1=rtio_external_clk,
45+
i_S=self._clock_sel.storage,
46+
o_O=self.cd_rtio.clk)
8047

81-
# ISE infers correct period constraints for cd_rtio.clk from
82-
# the internal clock. The first two TIGs target just the BUFGMUX.
8348
platform.add_platform_command("""
84-
NET "sys_clk" TNM_NET = "GRPsys_clk";
85-
NET "{ext_clk}" TNM_NET = "GRPext_clk";
86-
TIMESPEC "TSfix_ise1" = FROM "GRPsys_clk" TO "GRPext_clk" TIG;
8749
NET "{int_clk}" TNM_NET = "GRPint_clk";
50+
NET "sys_clk" TNM_NET = "GRPsys_clk";
51+
TIMESPEC "TSfix_ise1" = FROM "GRPint_clk" TO "GRPsys_clk" TIG;
8852
TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPint_clk" TIG;
89-
NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
90-
TIMESPEC "TSfix_ise3" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
91-
TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
92-
""", ext_clk=rtio_external_clk, int_clk=rtio_internal_clk,
93-
rtio_clk=self.cd_rtio.clk)
53+
""", int_clk=rtio_internal_clk)
9454

9555

9656
class NIST_QC1(BaseSoC, AMPSoC):
@@ -130,22 +90,16 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
13090
platform.request("ttl_h_tx_en").eq(1)
13191
]
13292

133-
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
134-
13593
# RTIO channels
13694
rtio_channels = []
137-
# pmt1 can run on a 8x serdes if pmt0 is not used
13895
for i in range(2):
139-
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
140-
self.rtio_crg.rtiox4_stb)
96+
phy = ttl_simple.Inout(platform.request("pmt", i))
14197
self.submodules += phy
14298
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512,
14399
ofifo_depth=4))
144100

145-
# ttl2 can run on a 8x serdes if xtrig is not used
146101
for i in range(15):
147-
phy = ttl_serdes_spartan6.Output_4X(platform.request("ttl", i),
148-
self.rtio_crg.rtiox4_stb)
102+
phy = ttl_simple.Output(platform.request("ttl", i))
149103
self.submodules += phy
150104
rtio_channels.append(rtio.Channel.from_phy(phy, ofifo_depth=256))
151105

@@ -175,6 +129,7 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
175129
ififo_depth=4))
176130

177131
# RTIO core
132+
self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
178133
self.submodules.rtio = rtio.RTIO(rtio_channels)
179134
self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
180135
self.add_constant("DDS_RTIO_CLK_RATIO", 8 >> self.rtio.fine_ts_width)

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