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cores/liteeth_mini: adapt all phys to new migen
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enjoy-digital committed Oct 23, 2015
1 parent 197e5cf commit 7459419
Showing 3 changed files with 6 additions and 12 deletions.
10 changes: 3 additions & 7 deletions misoc/cores/liteeth_mini/phy/gmii.py
Original file line number Diff line number Diff line change
@@ -92,11 +92,7 @@ def __init__(self, clock_pads, pads, with_hw_init_reset, mii_mode=0):
class LiteEthPHYGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads,
pads,
with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYGMIITX(pads),
"eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYGMIIRX(pads),
"eth_rx")
self.submodules.crg = LiteEthPHYGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source
4 changes: 2 additions & 2 deletions misoc/cores/liteeth_mini/phy/mii.py
Original file line number Diff line number Diff line change
@@ -105,6 +105,6 @@ class LiteEthPHYMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8
self.submodules.crg = LiteEthPHYMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = RenameClockDomains(LiteEthPHYMIITX(pads), "eth_tx")
self.submodules.rx = RenameClockDomains(LiteEthPHYMIIRX(pads), "eth_rx")
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_tx")(LiteEthPHYMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source
4 changes: 1 addition & 3 deletions misoc/cores/liteeth_mini/phy/s6rgmii.py
Original file line number Diff line number Diff line change
@@ -155,9 +155,7 @@ def __init__(self, clock_pads, pads, with_hw_init_reset):
class LiteEthPHYRGMII(Module, AutoCSR):
def __init__(self, clock_pads, pads, with_hw_init_reset=True):
self.dw = 8
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
pads,
with_hw_init_reset)
self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads, pads, with_hw_init_reset)
self.submodules.tx = ClockDomainsRenamer("eth_tx")(LiteEthPHYRGMIITX(pads))
self.submodules.rx = ClockDomainsRenamer("eth_rx")(LiteEthPHYRGMIIRX(pads))
self.sink, self.source = self.tx.sink, self.rx.source

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