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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: e557d7e2dfec
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on May 13, 2015

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Showing with 1 addition and 15 deletions.
  1. +1 −15 artiq/gateware/ad9858.py
16 changes: 1 addition & 15 deletions artiq/gateware/ad9858.py
Original file line number Diff line number Diff line change
@@ -1,25 +1,11 @@
from migen.fhdl.std import *
from migen.genlib.fsm import *
from migen.genlib.misc import WaitTimer
from migen.bus import wishbone
from migen.bus.transactions import *
from migen.sim.generic import run_simulation


class WaitTimer(Module):
def __init__(self, t):
self.wait = Signal()
self.done = Signal()

# # #

count = Signal(bits_for(t), reset=t)
self.comb += self.done.eq(count == 0)
self.sync += \
If(self.wait,
If(~self.done, count.eq(count - 1))
).Else(count.eq(count.reset))


class AD9858(Module):
"""Wishbone interface to the AD9858 DDS chip.