Skip to content

Commit fb5397a

Browse files
enjoy-digitalenjoy-digital
committedMay 9, 2015
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
·
0.120.1
1 parent 1fd1895 commit fb5397a

File tree

8 files changed

+14
-14
lines changed

8 files changed

+14
-14
lines changed
 

Diff for: ‎misoclib/com/liteeth/example_designs/targets/base.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
from misoclib.tools.litescope.frontend.la import LiteScopeLA
88
from misoclib.tools.litescope.core.port import LiteScopeTerm
99

10-
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
10+
from misoclib.com.uart.wishbone import UARTWishboneBridge
1111

1212
from misoclib.com.liteeth.common import *
1313
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII

Diff for: ‎misoclib/com/litepcie/example_designs/targets/dma.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
from misoclib.soc import SoC
88
from misoclib.tools.litescope.common import *
99

10-
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
10+
from misoclib.com.uart.wishbone import UARTWishboneBridge
1111

1212
from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
1313
from misoclib.com.litepcie.core import Endpoint

Diff for: ‎misoclib/com/liteusb/frontend/wishbone.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
from migen.fhdl.std import *
22

33
from misoclib.com.liteusb.common import *
4-
from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
4+
from misoclib.tools.wishbone import WishboneStreamingBridge
55

6-
class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
6+
class LiteUSBWishboneBridge(WishboneStreamingBridge):
77
def __init__(self, port, clk_freq):
8-
LiteScopeWishboneBridge.__init__(self, port, clk_freq)
8+
WishboneStreamingBridge.__init__(self, port, clk_freq)
99
self.comb += port.sink.dst.eq(port.tag)

Diff for: ‎misoclib/com/uart/frontend/__init__.py

Whitespace-only changes.

Diff for: ‎misoclib/com/uart/frontend/wishbone.py renamed to ‎misoclib/com/uart/wishbone.py

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
from migen.fhdl.std import *
22

3-
from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
3+
from misoclib.tools.wishbone import WishboneStreamingBridge
44
from misoclib.com.uart.phy.serial import UARTPHYSerial
55

6-
class UARTWishboneBridge(LiteScopeWishboneBridge):
6+
class UARTWishboneBridge(WishboneStreamingBridge):
77
def __init__(self, pads, clk_freq, baudrate=115200):
88
self.submodules.phy = UARTPHYSerial(pads, clk_freq, baudrate)
9-
LiteScopeWishboneBridge.__init__(self, self.phy, clk_freq)
9+
WishboneStreamingBridge.__init__(self, self.phy, clk_freq)

Diff for: ‎misoclib/mem/litesata/example_designs/targets/bist.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
from misoclib.tools.litescope.frontend.la import LiteScopeLA
1010
from misoclib.tools.litescope.core.port import LiteScopeTerm
1111

12-
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
12+
from misoclib.com.uart.wishbone import UARTWishboneBridge
1313

1414
from misoclib.mem.litesata.common import *
1515
from misoclib.mem.litesata.phy import LiteSATAPHY

Diff for: ‎misoclib/tools/litescope/example_designs/targets/simple.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
from misoclib.tools.litescope.frontend.io import LiteScopeIO
88
from misoclib.tools.litescope.frontend.la import LiteScopeLA
99

10-
from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
10+
from misoclib.com.uart.wishbone import UARTWishboneBridge
1111

1212
class LiteScopeSoC(SoC, AutoCSR):
1313
csr_map = {

Diff for: ‎misoclib/tools/litescope/frontend/wishbone.py renamed to ‎misoclib/tools/wishbone.py

+4-4
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,12 @@
1-
from misoclib.tools.litescope.common import *
1+
from migen.fhdl.std import *
22
from migen.bus import wishbone
3-
from migen.genlib.misc import chooser
3+
from migen.genlib.misc import chooser, Counter, Timeout
44
from migen.genlib.record import Record
5+
from migen.genlib.fsm import FSM, NextState
56
from migen.flow.actor import Sink, Source
67

7-
from misoclib.com.uart.phy.serial import UARTPHYSerial
88

9-
class LiteScopeWishboneBridge(Module):
9+
class WishboneStreamingBridge(Module):
1010
cmds = {
1111
"write": 0x01,
1212
"read": 0x02

0 commit comments

Comments
 (0)
Please sign in to comment.