uart: rename wishbone to bridge

enjoy-digital · enjoy-digital · commit a99aa9c7fd56 · 2015-05-09T16:24:28.000+02:00
diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -7,7 +7,7 @@
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -7,7 +7,7 @@
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint
diff --git a/misoclib/com/uart/bridge.py b/misoclib/com/uart/bridge.py
diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py
@@ -9,7 +9,7 @@
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 from misoclib.mem.litesata.common import *
 from misoclib.mem.litesata.phy import LiteSATAPHY
diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py
@@ -7,7 +7,7 @@
 from misoclib.tools.litescope.frontend.io import LiteScopeIO
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 
-from misoclib.com.uart.wishbone import UARTWishboneBridge
+from misoclib.com.uart.bridge import UARTWishboneBridge
 
 class LiteScopeSoC(SoC, AutoCSR):
     csr_map = {
