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enjoy-digitalenjoy-digital
committedMay 12, 2015
cores: replace Timeout with new WaitTimer
·
0.120.1
1 parent a99aa9c commit d9b15e6

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9 files changed

+54
-71
lines changed

9 files changed

+54
-71
lines changed
 

‎misoclib/com/liteeth/common.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
from migen.genlib.resetsync import AsyncResetSynchronizer
66
from migen.genlib.record import *
77
from migen.genlib.fsm import FSM, NextState
8-
from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, Timeout
8+
from migen.genlib.misc import chooser, reverse_bytes, FlipFlop, Counter, WaitTimer
99
from migen.flow.actor import *
1010
from migen.actorlib.structuring import Converter, Pipeline
1111
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO

‎misoclib/com/liteeth/core/arp/__init__.py

+8-10
Original file line numberDiff line numberDiff line change
@@ -146,13 +146,13 @@ def __init__(self, clk_freq, max_requests=8):
146146

147147
# # #
148148

149-
request_timeout = Timeout(clk_freq//10)
149+
request_timer = WaitTimer(clk_freq//10)
150150
request_counter = Counter(max=max_requests)
151151
request_pending = FlipFlop()
152152
request_ip_address = FlipFlop(32)
153-
self.submodules += request_timeout, request_counter, request_pending, request_ip_address
153+
self.submodules += request_timer, request_counter, request_pending, request_ip_address
154154
self.comb += [
155-
request_timeout.ce.eq(request_pending.q),
155+
request_timer.wait.eq(request_pending.q & ~request_counter.ce),
156156
request_pending.d.eq(1),
157157
request_ip_address.d.eq(request.ip_address)
158158
]
@@ -164,8 +164,8 @@ def __init__(self, clk_freq, max_requests=8):
164164
cached_valid = Signal()
165165
cached_ip_address = Signal(32)
166166
cached_mac_address = Signal(48)
167-
cached_timeout = Timeout(clk_freq*10)
168-
self.submodules += cached_timeout
167+
cached_timer = WaitTimer(clk_freq*10)
168+
self.submodules += cached_timer
169169

170170
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
171171
fsm.act("IDLE",
@@ -177,7 +177,7 @@ def __init__(self, clk_freq, max_requests=8):
177177
NextState("UPDATE_TABLE"),
178178
).Elif(request_counter.value == max_requests-1,
179179
NextState("PRESENT_RESPONSE")
180-
).Elif(request.stb | (request_pending.q & request_timeout.reached),
180+
).Elif(request.stb | (request_pending.q & request_timer.done),
181181
NextState("CHECK_TABLE")
182182
)
183183
)
@@ -199,10 +199,9 @@ def __init__(self, clk_freq, max_requests=8):
199199
cached_valid.eq(1),
200200
cached_ip_address.eq(sink.ip_address),
201201
cached_mac_address.eq(sink.mac_address),
202-
cached_timeout.reset.eq(1)
203202
).Else(
204-
cached_timeout.ce.eq(1),
205-
If(cached_timeout.reached,
203+
cached_timer.wait.eq(1),
204+
If(cached_timer.done,
206205
cached_valid.eq(0)
207206
)
208207
)
@@ -230,7 +229,6 @@ def __init__(self, clk_freq, max_requests=8):
230229
source.request.eq(1),
231230
source.ip_address.eq(request_ip_address.q),
232231
If(source.ack,
233-
request_timeout.reset.eq(1),
234232
request_counter.reset.eq(request.stb),
235233
request_counter.ce.eq(1),
236234
request_pending.ce.eq(1),

‎misoclib/com/liteusb/core/packet.py

+6-9
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from misoclib.com.liteusb.common import *
22
from migen.actorlib.structuring import Pack, Unpack
3-
from migen.genlib.misc import Timeout
3+
from migen.genlib.misc import WaitTimer
44

55
class LiteUSBPacketizer(Module):
66
def __init__(self):
@@ -116,16 +116,13 @@ def __init__(self, clk_freq, timeout=10):
116116
header_pack.source.ack.eq(1),
117117
)
118118

119-
self.submodules.timeout = Timeout(clk_freq*timeout)
120-
self.comb += [
121-
self.timeout.reset.eq(fsm.ongoing("IDLE")),
122-
self.timeout.ce.eq(1)
123-
]
119+
self.submodules.timer = WaitTimer(clk_freq*timeout)
120+
self.comb += self.timer.wait.eq(~fsm.ongoing("IDLE"))
124121

125122
fsm.act("RECEIVE_HEADER",
126123
header_pack.sink.stb.eq(sink.stb),
127124
header_pack.sink.payload.eq(sink.payload),
128-
If(self.timeout.reached,
125+
If(self.timer.done,
129126
NextState("IDLE")
130127
).Elif(header_pack.source.stb,
131128
NextState("COPY")
@@ -134,7 +131,7 @@ def __init__(self, clk_freq, timeout=10):
134131
)
135132
)
136133

137-
self.comb += header_pack.reset.eq(self.timeout.reached)
134+
self.comb += header_pack.reset.eq(self.timer.done)
138135

139136
sop = Signal()
140137
eop = Signal()
@@ -146,7 +143,7 @@ def __init__(self, clk_freq, timeout=10):
146143
source.eop.eq(eop),
147144
source.data.eq(sink.data),
148145
sink.ack.eq(source.ack),
149-
If((source.stb & source.ack & eop) | self.timeout.reached,
146+
If((source.stb & source.ack & eop) | self.timer.done
150147
NextState("IDLE")
151148
)
152149
)

‎misoclib/mem/litesata/common.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
from migen.genlib.resetsync import *
66
from migen.genlib.fsm import *
77
from migen.genlib.record import *
8-
from migen.genlib.misc import chooser, optree, Counter, Timeout
8+
from migen.genlib.misc import chooser, optree, Counter, WaitTimer
99
from migen.genlib.cdc import *
1010
from migen.flow.actor import *
1111
from migen.flow.plumbing import Multiplexer, Demultiplexer

‎misoclib/mem/litesata/phy/ctrl.py

+10-12
Original file line numberDiff line numberDiff line change
@@ -15,9 +15,9 @@ def __init__(self, trx, crg, clk_freq):
1515
sink.ack.eq(1)
1616
]
1717

18-
retry_timeout = Timeout(self.us(10000))
19-
align_timeout = Timeout(self.us(873))
20-
self.submodules += align_timeout, retry_timeout
18+
retry_timer = WaitTimer(self.us(10000))
19+
align_timer = WaitTimer(self.us(873))
20+
self.submodules += align_timer, retry_timer
2121

2222
align_detect = Signal()
2323
non_align_cnt = Signal(4)
@@ -26,11 +26,9 @@ def __init__(self, trx, crg, clk_freq):
2626

2727
self.fsm = fsm = InsertReset(FSM(reset_state="RESET"))
2828
self.submodules += fsm
29-
self.comb += fsm.reset.eq(retry_timeout.reached | align_timeout.reached)
29+
self.comb += fsm.reset.eq(retry_timer.done | align_timer.done)
3030
fsm.act("RESET",
3131
trx.tx_idle.eq(1),
32-
retry_timeout.reset.eq(1),
33-
align_timeout.reset.eq(1),
3432
non_align_counter.reset.eq(1),
3533
If(crg.ready,
3634
NextState("COMINIT")
@@ -45,14 +43,14 @@ def __init__(self, trx, crg, clk_freq):
4543
)
4644
fsm.act("AWAIT_COMINIT",
4745
trx.tx_idle.eq(1),
48-
retry_timeout.ce.eq(1),
46+
retry_timer.wait.eq(1),
4947
If(trx.rx_cominit_stb,
5048
NextState("AWAIT_NO_COMINIT")
5149
)
5250
)
5351
fsm.act("AWAIT_NO_COMINIT",
5452
trx.tx_idle.eq(1),
55-
retry_timeout.reset.eq(1),
53+
retry_timer.wait.eq(1),
5654
If(~trx.rx_cominit_stb,
5755
NextState("CALIBRATE")
5856
)
@@ -70,7 +68,7 @@ def __init__(self, trx, crg, clk_freq):
7068
)
7169
fsm.act("AWAIT_COMWAKE",
7270
trx.tx_idle.eq(1),
73-
retry_timeout.ce.eq(1),
71+
retry_timer.wait.eq(1),
7472
If(trx.rx_comwake_stb,
7573
NextState("AWAIT_NO_COMWAKE")
7674
)
@@ -85,7 +83,7 @@ def __init__(self, trx, crg, clk_freq):
8583
trx.tx_idle.eq(0),
8684
source.data.eq(0x4A4A4A4A), # D10.2
8785
source.charisk.eq(0b0000),
88-
align_timeout.ce.eq(1),
86+
align_timer.wait.eq(1),
8987
If(~trx.rx_idle,
9088
NextState("AWAIT_ALIGN"),
9189
crg.tx_reset.eq(1),
@@ -97,15 +95,15 @@ def __init__(self, trx, crg, clk_freq):
9795
source.data.eq(0x4A4A4A4A), # D10.2
9896
source.charisk.eq(0b0000),
9997
trx.rx_align.eq(1),
100-
align_timeout.ce.eq(1),
98+
align_timer.wait.eq(1),
10199
If(align_detect & ~trx.rx_idle,
102100
NextState("SEND_ALIGN")
103101
)
104102
)
105103
fsm.act("SEND_ALIGN",
106104
trx.tx_idle.eq(0),
107105
trx.rx_align.eq(1),
108-
align_timeout.ce.eq(1),
106+
align_timer.wait.eq(1),
109107
source.data.eq(primitives["ALIGN"]),
110108
source.charisk.eq(0b0001),
111109
If(sink.stb,

‎misoclib/mem/litesata/phy/k7/crg.py

+18-25
Original file line numberDiff line numberDiff line change
@@ -78,20 +78,17 @@ def __init__(self, pads, gtx, revision, clk_freq):
7878
# After configuration, GTX's resets have to stay low for at least 500ns
7979
# See AR43482
8080
startup_cycles = math.ceil(500*clk_freq/1000000000)
81-
startup_wait = Timeout(startup_cycles)
82-
self.submodules += startup_wait
83-
self.comb += [
84-
startup_wait.reset.eq(self.tx_reset | self.rx_reset),
85-
startup_wait.ce.eq(1)
86-
]
81+
startup_timer = WaitTimer(startup_cycles)
82+
self.submodules += startup_timer
83+
self.comb += startup_timer.wait.eq(~(self.tx_reset | self.rx_reset))
8784

8885
# TX Startup FSM
8986
self.tx_ready = Signal()
9087
tx_startup_fsm = InsertReset(FSM(reset_state="IDLE"))
9188
self.submodules += tx_startup_fsm
9289
# Wait 500ns of AR43482
9390
tx_startup_fsm.act("IDLE",
94-
If(startup_wait.reached,
91+
If(startup_timer.done,
9592
NextState("RESET_ALL"),
9693
)
9794
)
@@ -144,12 +141,11 @@ def __init__(self, pads, gtx, revision, clk_freq):
144141
self.tx_ready.eq(1)
145142
)
146143

147-
tx_ready_timeout = Timeout(1*clk_freq//1000)
148-
self.submodules += tx_ready_timeout
144+
tx_ready_timer = WaitTimer(1*clk_freq//1000)
145+
self.submodules += tx_ready_timer
149146
self.comb += [
150-
tx_ready_timeout.reset.eq(self.tx_reset | self.tx_ready),
151-
tx_ready_timeout.ce.eq(~self.tx_ready),
152-
tx_startup_fsm.reset.eq(self.tx_reset | tx_ready_timeout.reached),
147+
tx_ready_timer.wait.eq(~self.tx_ready),
148+
tx_startup_fsm.reset.eq(self.tx_reset | tx_ready_timer.done),
153149
]
154150

155151

@@ -158,14 +154,12 @@ def __init__(self, pads, gtx, revision, clk_freq):
158154
rx_startup_fsm = InsertReset(FSM(reset_state="IDLE"))
159155
self.submodules += rx_startup_fsm
160156

161-
cdr_stable = Timeout(2048)
162-
self.submodules += cdr_stable
163-
self.comb += cdr_stable.ce.eq(1),
157+
cdr_stable_timer = WaitTimer(2048)
158+
self.submodules += cdr_stable_timer
164159

165160
# Wait 500ns of AR43482
166161
rx_startup_fsm.act("IDLE",
167-
cdr_stable.reset.eq(1),
168-
If(startup_wait.reached,
162+
If(startup_timer.done,
169163
NextState("RESET_GTX"),
170164
)
171165
)
@@ -178,16 +172,16 @@ def __init__(self, pads, gtx, revision, clk_freq):
178172
rx_startup_fsm.act("WAIT_CPLL",
179173
gtx.gtrxreset.eq(1),
180174
If(gtx.cplllock,
181-
NextState("RELEASE_GTX"),
182-
cdr_stable.reset.eq(1)
175+
NextState("RELEASE_GTX")
183176
)
184177
)
185178
# Release GTX reset and wait for GTX resetdone
186179
# (from UG476, GTX is reseted on falling edge
187180
# of gttxreset)
188181
rx_startup_fsm.act("RELEASE_GTX",
189182
gtx.rxuserrdy.eq(1),
190-
If(gtx.rxresetdone & cdr_stable.reached,
183+
cdr_stable_timer.wait.eq(1),
184+
If(gtx.rxresetdone & cdr_stable_timer.done,
191185
NextState("ALIGN")
192186
)
193187
)
@@ -209,12 +203,11 @@ def __init__(self, pads, gtx, revision, clk_freq):
209203
self.rx_ready.eq(1)
210204
)
211205

212-
rx_ready_timeout = Timeout(1*clk_freq//1000)
213-
self.submodules += rx_ready_timeout
206+
rx_ready_timer = WaitTimer(1*clk_freq//1000)
207+
self.submodules += rx_ready_timer
214208
self.comb += [
215-
rx_ready_timeout.reset.eq(self.rx_reset | self.rx_ready),
216-
rx_ready_timeout.ce.eq(~self.rx_ready),
217-
rx_startup_fsm.reset.eq(self.rx_reset | rx_ready_timeout.reached),
209+
rx_ready_timer.wait.eq(~self.rx_ready),
210+
rx_startup_fsm.reset.eq(self.rx_reset | rx_ready_timer.done),
218211
]
219212

220213
# Ready

‎misoclib/mem/litesata/phy/k7/trx.py

+3-6
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,14 @@ def __init__(self, i, o):
2424
class _LowPassFilter(Module):
2525
def __init__(self, i, o, cycles):
2626
i_d = Signal()
27-
self.submodules.timeout = Timeout(cycles)
27+
self.submodules.timer = WaitTimer(cycles)
2828
self.sync += [
2929
i_d.eq(i),
30-
If(self.timeout.reached,
30+
If(self.timer.done,
3131
o.eq(i_d)
3232
)
3333
]
34-
self.comb += [
35-
self.timeout.reset.eq(i != i_d),
36-
self.timeout.ce.eq(1)
37-
]
34+
self.comb += self.timer.wait.eq(i == i_d)
3835

3936

4037
class K7LiteSATAPHYTRX(Module):

‎misoclib/tools/litescope/common.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
from migen.bank.description import *
33
from migen.genlib.fsm import FSM, NextState
44
from migen.flow.actor import *
5-
from migen.genlib.misc import Counter, Timeout
5+
from migen.genlib.misc import Counter
66
from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
77
from migen.flow.plumbing import Buffer
88
from migen.fhdl.specials import Memory

‎misoclib/tools/wishbone.py

+6-6
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from migen.fhdl.std import *
22
from migen.bus import wishbone
3-
from migen.genlib.misc import chooser, Counter, Timeout
3+
from migen.genlib.misc import chooser, Counter, WaitTimer
44
from migen.genlib.record import Record
55
from migen.genlib.fsm import FSM, NextState
66
from migen.flow.actor import Sink, Source
@@ -46,15 +46,13 @@ def __init__(self, phy, clk_freq):
4646
]
4747

4848
fsm = InsertReset(FSM(reset_state="IDLE"))
49-
timeout = Timeout(clk_freq//10)
50-
self.submodules += fsm, timeout
49+
timer = WaitTimer(clk_freq//10)
50+
self.submodules += fsm, timer
5151
self.comb += [
52-
timeout.ce.eq(1),
53-
fsm.reset.eq(timeout.reached),
52+
fsm.reset.eq(timer.done),
5453
phy.source.ack.eq(1)
5554
]
5655
fsm.act("IDLE",
57-
timeout.reset.eq(1),
5856
If(phy.source.stb,
5957
cmd_ce.eq(1),
6058
If((phy.source.data == self.cmds["write"]) |
@@ -140,6 +138,8 @@ def __init__(self, phy, clk_freq):
140138
)
141139
)
142140

141+
self.comb += timer.wait.eq(~fsm.ongoing("IDLE"))
142+
143143
if phy.sink.description.packetized:
144144
self.comb += [
145145
phy.sink.sop.eq((byte_counter.value == 0) & (word_counter.value == 0)),

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