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  • 2 commits
  • 25 files changed
  • 1 contributor

Commits on May 23, 2015

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21 changes: 0 additions & 21 deletions misoclib/mem/litesata/__init__.py
Original file line number Diff line number Diff line change
@@ -1,21 +0,0 @@
from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.phy import *
from misoclib.mem.litesata.core import *
from misoclib.mem.litesata.frontend import *

from migen.bank.description import *


class LiteSATA(Module, AutoCSR):
def __init__(self, phy, buffer_depth=2*fis_max_dwords,
with_bist=False, with_bist_csr=False):
# phy
self.phy = phy

# core
self.submodules.core = LiteSATACore(self.phy, buffer_depth)

# frontend
self.submodules.crossbar = LiteSATACrossbar(self.core)
if with_bist:
self.submodules.bist = LiteSATABIST(self.crossbar, with_bist_csr)
2 changes: 1 addition & 1 deletion misoclib/mem/litesata/core/__init__.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@


class LiteSATACore(Module):
def __init__(self, phy, buffer_depth):
def __init__(self, phy, buffer_depth=2*fis_max_dwords):
self.submodules.link = LiteSATALink(phy, buffer_depth)
self.submodules.transport = LiteSATATransport(self.link)
self.submodules.command = LiteSATACommand(self.transport)
13 changes: 10 additions & 3 deletions misoclib/mem/litesata/core/link/__init__.py
Original file line number Diff line number Diff line change
@@ -41,6 +41,7 @@ def __init__(self, phy):

# datas / primitives mux
insert = Signal(32)
copy = Signal()
self.comb += [
If(self.from_rx.insert,
cont.sink.stb.eq(1),
@@ -51,7 +52,7 @@ def __init__(self, phy):
cont.sink.stb.eq(1),
cont.sink.data.eq(insert),
cont.sink.charisk.eq(0x0001),
).Elif(fsm.ongoing("COPY"),
).Elif(copy,
cont.sink.stb.eq(scrambler.source.stb),
cont.sink.data.eq(scrambler.source.d),
scrambler.source.ack.eq(cont.sink.ack),
@@ -87,6 +88,7 @@ def __init__(self, phy):
)
)
fsm.act("COPY",
copy.eq(1),
If(self.from_rx.det == primitives["HOLD"],
insert.eq(primitives["HOLDA"]),
).Elif(~scrambler.source.stb,
@@ -145,12 +147,15 @@ def __init__(self, phy):
crc = LiteSATACRCChecker(link_description(32))
self.submodules += crc

idle = Signal()
copy = Signal()

sop = Signal()
eop = Signal()
self.sync += \
If(fsm.ongoing("IDLE"),
If(idle,
sop.eq(1),
).Elif(fsm.ongoing("COPY"),
).Elif(copy,
If(scrambler.sink.stb & scrambler.sink.ack,
sop.eq(0)
)
@@ -177,6 +182,7 @@ def __init__(self, phy):

# FSM
fsm.act("IDLE",
idle.eq(1),
scrambler.reset.eq(1),
If(det == primitives["X_RDY"],
NextState("RDY")
@@ -199,6 +205,7 @@ def __init__(self, phy):
scrambler.sink.eop.eq(eop)
]
fsm.act("COPY",
copy.eq(1),
scrambler.sink.stb.eq(cont.source.stb & ((det == 0) | eop)),
insert.eq(primitives["R_IP"]),
If(det == primitives["HOLD"],
20 changes: 8 additions & 12 deletions misoclib/mem/litesata/example_designs/make.py
Original file line number Diff line number Diff line change
@@ -94,10 +94,10 @@ def _get_args():
print(" "+a)
sys.exit(1)


revision = soc.sata_phy.revision
has_bist = hasattr(soc.sata, "bist")
user_ports = len(soc.sata.crossbar.users)
try:
revision = soc.sata_phy.revision
except:
revision = soc.sata_phy0.revision

print("""
__ _ __ _______ _________
@@ -111,13 +111,9 @@ def _get_args():
====== Building options: ======
{} / {} Gbps
System Clk: {} MHz (min: {} MHz)
User ports: {}
BIST: {}
===============================""".format(
revision.replace("sata_", "SATA "), bitrates[revision],
soc.clk_freq/1000000, frequencies[revision],
user_ports,
has_bist
soc.clk_freq/1000000, frequencies[revision]
)
)

@@ -145,9 +141,9 @@ def _get_args():
soc = soc.get_fragment()
platform.finalize(soc)
so = {
NoRetiming: XilinxNoRetiming,
MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
NoRetiming: XilinxNoRetiming,
MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer
}
v_output = verilog.convert(soc, ios, special_overrides=so)
v_output.write("build/litesata.v")
35 changes: 23 additions & 12 deletions misoclib/mem/litesata/example_designs/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -2,13 +2,33 @@
from mibuild.platforms import kc705

_sata_io = [
("sata", 0,
("sata_clocks", 0,
Subsignal("refclk_p", Pins("HPC:GBTCLK0_M2C_P")),
Subsignal("refclk_n", Pins("HPC:GBTCLK0_M2C_N")),
Subsignal("refclk_n", Pins("HPC:GBTCLK0_M2C_N"))
),
("sata", 0,
Subsignal("txp", Pins("HPC:DP0_C2M_P")),
Subsignal("txn", Pins("HPC:DP0_C2M_N")),
Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
Subsignal("rxn", Pins("HPC:DP0_M2C_N")),
Subsignal("rxn", Pins("HPC:DP0_M2C_N"))
),
("sata", 1,
Subsignal("txp", Pins("HPC:DP1_C2M_P")),
Subsignal("txn", Pins("HPC:DP1_C2M_N")),
Subsignal("rxp", Pins("HPC:DP1_M2C_P")),
Subsignal("rxn", Pins("HPC:DP1_M2C_N"))
),
("sata", 2,
Subsignal("txp", Pins("HPC:DP2_C2M_P")),
Subsignal("txn", Pins("HPC:DP2_C2M_N")),
Subsignal("rxp", Pins("HPC:DP2_M2C_P")),
Subsignal("rxn", Pins("HPC:DP2_M2C_N"))
),
("sata", 3,
Subsignal("txp", Pins("HPC:DP3_C2M_P")),
Subsignal("txn", Pins("HPC:DP3_C2M_N")),
Subsignal("rxp", Pins("HPC:DP3_M2C_P")),
Subsignal("rxn", Pins("HPC:DP3_M2C_N"))
)
]

@@ -28,15 +48,6 @@ def do_finalize(self, fragment):
except ConstraintError:
pass
self.add_platform_command("""
create_clock -name sys_clk -period 6 [get_nets sys_clk]
create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]
""")
67 changes: 36 additions & 31 deletions misoclib/mem/litesata/example_designs/targets/bist.py
Original file line number Diff line number Diff line change
@@ -13,7 +13,9 @@

from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.phy import LiteSATAPHY
from misoclib.mem.litesata import LiteSATA
from misoclib.mem.litesata.core import LiteSATACore
from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
from misoclib.mem.litesata.frontend.bist import LiteSATABIST


class _CRG(Module):
@@ -53,41 +55,31 @@ def __init__(self, platform):


class BISTLeds(Module):
def __init__(self, platform, sata_phy):
# 1Hz blinking leds (sata_rx and sata_tx clocks)
sata_rx_led = platform.request("user_led", 0)
sata_tx_led = platform.request("user_led", 1)
def __init__(self, platform, sata_phys):
for i, sata_phy in enumerate(sata_phys):
# 1Hz blinking leds (sata_rx and sata_tx clocks)
rx_led = platform.request("user_led", 2*i)

sata_rx_cnt = Signal(32)
sata_tx_cnt = Signal(32)
rx_cnt = Signal(32)

sata_freq = int(frequencies[sata_phy.revision]*1000*1000)
freq = int(frequencies[sata_phy.revision]*1000*1000)

self.sync.sata_rx += \
If(sata_rx_cnt == 0,
sata_rx_led.eq(~sata_rx_led),
sata_rx_cnt.eq(sata_freq//2)
).Else(
sata_rx_cnt.eq(sata_rx_cnt-1)
)
self.sync.sata_rx += \
If(rx_cnt == 0,
rx_led.eq(~rx_led),
rx_cnt.eq(freq//2)
).Else(
rx_cnt.eq(rx_cnt-1)
)

self.sync.sata_tx += \
If(sata_tx_cnt == 0,
sata_tx_led.eq(~sata_tx_led),
sata_tx_cnt.eq(sata_freq//2)
).Else(
sata_tx_cnt.eq(sata_tx_cnt-1)
)

# ready leds (crg and ctrl)
self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready)
self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready)
# ready leds
self.comb += platform.request("user_led", 2*i+1).eq(sata_phy.ctrl.ready)


class BISTSoC(SoC, AutoCSR):
default_platform = "kc705"
csr_map = {
"sata": 10,
"sata_bist": 16
}
csr_map.update(SoC.csr_map)
def __init__(self, platform):
@@ -104,16 +96,29 @@ def __init__(self, platform):
self.submodules.crg = _CRG(platform)

# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata", 0), "sata_gen2", clk_freq)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar, with_csr=True)

# Status Leds
self.submodules.leds = BISTLeds(platform, self.sata_phy)
self.submodules.leds = BISTLeds(platform, [self.sata_phy])

platform.add_platform_command("""
create_clock -name sys_clk -period 6 [get_nets sys_clk]
create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk]
create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]
set_false_path -from [get_clocks sata_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sata_tx_clk] -to [get_clocks sys_clk]
""")

class BISTSoCDevel(BISTSoC, AutoCSR):
csr_map = {
"la": 20
"la": 17
}
csr_map.update(BISTSoC.csr_map)
def __init__(self, platform):
35 changes: 22 additions & 13 deletions misoclib/mem/litesata/example_designs/targets/core.py
Original file line number Diff line number Diff line change
@@ -2,22 +2,31 @@

from targets import *

from misoclib.soc import SoC

from misoclib.mem.litesata.common import *
from misoclib.mem.litesata.phy import LiteSATAPHY
from misoclib.mem.litesata import LiteSATA
from misoclib.mem.litesata.core import LiteSATACore
from misoclib.mem.litesata.frontend.crossbar import LiteSATACrossbar
from misoclib.mem.litesata.frontend.bist import LiteSATABIST


class LiteSATACore(Module):
class Core(Module):
default_platform = "verilog_backend"
def __init__(self, platform, clk_freq=166*1000000, nports=4):
def __init__(self, platform, clk_freq=166*1000000, with_bist=True, nports=4):
self.clk_freq = clk_freq

# SATA PHY/Core/Frontend
self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True)
self.submodules.sata_core = LiteSATACore(self.sata_phy)
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)

# BIST
if with_bist:
self.submodules.sata_bist = LiteSATABIST(self.sata_crossbar)

# Get user ports from crossbar
self.user_ports = self.sata.crossbar.get_ports(nports)
self.user_ports = self.sata_crossbar.get_ports(nports)

def get_ios(self):
ios = set()
@@ -35,16 +44,16 @@ def get_ios(self):
})

# BIST
if hasattr(self.sata, "bist"):
if hasattr(self, "sata_bist"):
for bist_unit in ["generator", "checker"]:
for signal in ["start", "sector", "count", "random", "done", "aborted", "errors"]:
ios = ios.union({getattr(getattr(self.sata.bist, bist_unit), signal)})
ios = ios.union({getattr(getattr(self.sata_bist, bist_unit), signal)})
ios = ios.union({
self.sata.bist.identify.start,
self.sata.bist.identify.done,
self.sata.bist.identify.source.stb,
self.sata.bist.identify.source.data,
self.sata.bist.identify.source.ack
self.sata_bist.identify.start,
self.sata_bist.identify.done,
self.sata_bist.identify.source.stb,
self.sata_bist.identify.source.data,
self.sata_bist.identify.source.ack
})

# User ports
@@ -62,4 +71,4 @@ def _iter_layout(layout):
ios = ios.union({obj})
return ios

default_subtarget = LiteSATACore
default_subtarget = Core
9 changes: 5 additions & 4 deletions misoclib/mem/litesata/example_designs/test/bist.py
Original file line number Diff line number Diff line change
@@ -72,7 +72,7 @@ class LiteSATABISTIdentifyDriver:
def __init__(self, regs, name):
self.regs = regs
self.name = name
for s in ["start", "done", "source_stb", "source_ack", "source_data"]:
for s in ["start", "done", "data_width", "source_stb", "source_ack", "source_data"]:
setattr(self, s, getattr(regs, name + "_identify_" + s))
self.data = []

@@ -189,11 +189,12 @@ def _get_args():
if not read_done:
retry += 1

ratio = identify.data_width.read()//32
print("sector={:d}({:d}MB) wr_speed={:4.2f}MB/s rd_speed={:4.2f}MB/s errors={:d} retry={:d}".format(
sector,
int(run_sectors*logical_sector_size/MB),
write_speed/MB,
read_speed/MB,
int(run_sectors*logical_sector_size/MB)*ratio,
write_speed/MB*ratio,
read_speed/MB*ratio,
write_errors + read_errors,
retry))
if random_addressing:
6 changes: 3 additions & 3 deletions misoclib/mem/litesata/example_designs/test/test_la.py
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
import sys
from tools import *
from test_bist import *
from litescope.software.driver.la import LiteScopeLADriver
from bist import *
from misoclib.tools.litescope.software.driver.la import LiteScopeLADriver


def main(wb):
la = LiteScopeLADriver(wb.regs, "la")
la = LiteScopeLADriver(wb.regs, "la", debug=True)
identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
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