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enjoy-digitalenjoy-digital
committedAug 4, 2015
liteeth: add rgmii phy
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0.120.1
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Diff for: ‎misoclib/com/liteeth/phy/__init__.py

+4
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,10 @@ def LiteEthPHY(clock_pads, pads, **kwargs):
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# This is a pure 1G PHY
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from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
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return LiteEthPHYGMII(clock_pads, pads, **kwargs)
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elif hasattr(pads, "rx_ctl"):
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# This is a 10/100/1G RGMII PHY
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from misoclib.com.liteeth.phy.rgmii import LiteEthPHYRGMII
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return LiteEthPHYRGMII(clock_pads, pads, **kwargs)
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elif flen(pads.tx_data) == 4:
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# This is a MII PHY
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from misoclib.com.liteeth.phy.mii import LiteEthPHYMII

Diff for: ‎misoclib/com/liteeth/phy/rgmii.py

+160
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,160 @@
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from migen.genlib.io import DDROutput
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from migen.genlib.misc import WaitTimer
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from migen.genlib.fsm import FSM, NextState
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from misoclib.com.liteeth.common import *
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class LiteEthPHYRGMIITX(Module):
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def __init__(self, pads, pads_register=True):
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self.sink = sink = Sink(eth_phy_description(8))
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# # #
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
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i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
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i_CE=1, i_S=0, i_R=0,
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i_D0=sink.stb, i_D1=sink.stb, o_Q=pads.tx_ctl,
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)
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for i in range(4):
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self.specials += Instance("ODDR2",
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p_DDR_ALIGNMENT="C0", p_INIT=0, p_SRTYPE="ASYNC",
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i_C0=ClockSignal("eth_tx"), i_C1=~ClockSignal("eth_tx"),
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i_CE=1, i_S=0, i_R=0,
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i_D0=sink.data[i], i_D1=sink.data[4+i], o_Q=pads.tx_data[i],
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)
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self.comb += sink.ack.eq(1)
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class LiteEthPHYRGMIIRX(Module):
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def __init__(self, pads):
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self.source = source = Source(eth_phy_description(8))
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# # #
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rx_ctl = Signal()
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rx_data = Signal(8)
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self.specials += Instance("IDDR2",
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p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
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i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
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i_CE=1, i_S=0, i_R=0,
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i_D=pads.rx_ctl, o_Q1=rx_ctl,
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)
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for i in range(4):
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self.specials += Instance("IDDR2",
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p_DDR_ALIGNMENT="C0", p_INIT_Q0=0, p_INIT_Q1=0, p_SRTYPE="ASYNC",
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i_C0=ClockSignal("eth_rx"), i_C1=~ClockSignal("eth_rx"),
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i_CE=1, i_S=0, i_R=0,
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i_D=pads.rx_data[i], o_Q0=rx_data[4+i], o_Q1=rx_data[i],
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)
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rx_ctl_d = Signal()
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self.sync += rx_ctl_d.eq(rx_ctl)
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sop = Signal()
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eop = Signal()
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self.comb += [
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sop.eq(rx_ctl & ~rx_ctl_d),
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eop.eq(~rx_ctl & rx_ctl_d)
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]
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self.sync += [
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source.stb.eq(rx_ctl),
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source.sop.eq(sop),
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source.data.eq(rx_data)
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]
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self.comb += source.eop.eq(eop)
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class LiteEthPHYRGMIICRG(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset):
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self._reset = CSRStorage()
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# # #
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self.clock_domains.cd_eth_rx = ClockDomain()
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self.clock_domains.cd_eth_tx = ClockDomain()
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# RX
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dcm_reset = Signal()
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dcm_locked = Signal()
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timer = WaitTimer(1024)
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fsm = FSM(reset_state="DCM_RESET")
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self.submodules += timer, fsm
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fsm.act("DCM_RESET",
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dcm_reset.eq(1),
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("DCM_WAIT")
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)
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)
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fsm.act("DCM_WAIT",
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timer.wait.eq(1),
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If(timer.done,
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NextState("DCM_CHECK_LOCK")
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)
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)
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fsm.act("DCM_CHECK_LOCK",
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If(~dcm_locked,
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NextState("DCM_RESET")
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)
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)
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clk90_rx = Signal()
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clk0_rx = Signal()
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clk0_rx_bufg = Signal()
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self.specials += Instance("DCM",
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i_CLKIN=clock_pads.rx,
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i_CLKFB=clk0_rx_bufg,
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o_CLK0=clk0_rx,
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o_CLK90=clk90_rx,
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o_LOCKED=dcm_locked,
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i_PSEN=0,
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i_PSCLK=0,
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i_PSINCDEC=0,
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i_RST=dcm_reset
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)
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self.specials += Instance("BUFG", i_I=clk0_rx, o_O=clk0_rx_bufg)
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self.specials += Instance("BUFG", i_I=clk90_rx, o_O=self.cd_eth_rx.clk)
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# TX
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self.specials += DDROutput(1, 0, clock_pads.tx, ClockSignal("eth_tx"))
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self.specials += Instance("BUFG", i_I=self.cd_eth_rx.clk, o_O=self.cd_eth_tx.clk)
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# Reset
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if with_hw_init_reset:
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reset = Signal()
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counter_done = Signal()
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self.submodules.counter = counter = Counter(max=512)
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self.comb += [
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counter_done.eq(counter.value == 256),
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counter.ce.eq(~counter_done),
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reset.eq(~counter_done | self._reset.storage)
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]
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else:
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reset = self._reset.storage
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self.comb += pads.rst_n.eq(~reset)
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self.specials += [
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AsyncResetSynchronizer(self.cd_eth_tx, reset),
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AsyncResetSynchronizer(self.cd_eth_rx, reset),
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]
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class LiteEthPHYRGMII(Module, AutoCSR):
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def __init__(self, clock_pads, pads, with_hw_init_reset=True):
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self.dw = 8
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self.submodules.crg = LiteEthPHYRGMIICRG(clock_pads,
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pads,
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with_hw_init_reset)
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self.submodules.tx = RenameClockDomains(LiteEthPHYRGMIITX(pads),
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"eth_tx")
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self.submodules.rx = RenameClockDomains(LiteEthPHYRGMIIRX(pads),
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"eth_rx")
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self.sink, self.source = self.tx.sink, self.rx.source

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