Skip to content

Commit

Permalink
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Merge master
Browse files Browse the repository at this point in the history
sbourdeauducq committed Jul 31, 2015
2 parents 9492802 + 89343ae commit ac134bb
Showing 163 changed files with 4,944 additions and 2,109 deletions.
18 changes: 10 additions & 8 deletions .travis.yml
Original file line number Diff line number Diff line change
@@ -13,26 +13,28 @@ before_install:
- . ./.travis/get-toolchain.sh
- . ./.travis/get-anaconda.sh
- source $HOME/miniconda/bin/activate py34
- conda install pip coverage binstar migen cython
- conda install -q pip coverage anaconda-client migen cython
- pip install coveralls
install:
- conda build conda/artiq
- conda install $HOME/miniconda/conda-bld/linux-64/artiq-*.tar.bz2
- conda install -q artiq --use-local
script:
- coverage run --source=artiq setup.py test
- make -C doc/manual html
after_success:
- binstar login --hostname $(hostname) --username $binstar_login --password $binstar_password
- binstar upload --user $binstar_login --channel dev --force $HOME/miniconda/conda-bld/linux-64/artiq-*.tar.bz2
- anaconda -q login --hostname $(hostname) --username $binstar_login --password $binstar_password
- anaconda -q upload --user $binstar_login --channel dev --force $HOME/miniconda/conda-bld/linux-64/artiq-*.tar.bz2
- anaconda -q logout
- coveralls
notifications:
email: false
email:
recipients:
- rjordens@nist.gov
on_success: always
on_failure: never
irc:
channels:
- chat.freenode.net#m-labs
template:
- "%{repository}#%{build_number} (%{branch} - %{commit} : %{author}): %{message}"
- "Build details : %{build_url}"
webhooks:
urls:
- https://webhooks.gitter.im/e/d26782523952bfa53814
2 changes: 1 addition & 1 deletion .travis/get-anaconda.sh
Original file line number Diff line number Diff line change
@@ -10,4 +10,4 @@ conda info -a
conda install conda-build jinja2
conda create -q -n py34 python=$TRAVIS_PYTHON_VERSION
conda config --add channels fallen
conda config --add channels https://conda.binstar.org/fallen/channel/dev
conda config --add channels https://conda.anaconda.org/fallen/channel/dev
21 changes: 13 additions & 8 deletions .travis/get-toolchain.sh
Original file line number Diff line number Diff line change
@@ -1,8 +1,7 @@
#!/bin/sh

packages="https://people.phys.ethz.ch/~robertjo/artiq-dev/or1k-gcc_20141105-1_amd64.deb
https://people.phys.ethz.ch/~robertjo/artiq-dev/or1k-binutils_20141105-1_amd64.deb
http://us.archive.ubuntu.com/ubuntu/pool/universe/i/iverilog/iverilog_0.9.7-1_amd64.deb"
packages="http://us.archive.ubuntu.com/ubuntu/pool/universe/i/iverilog/iverilog_0.9.7-1_amd64.deb"
archives="http://fehu.whitequark.org/files/binutils-or1k.tbz2 http://fehu.whitequark.org/files/llvm-or1k.tbz2"

mkdir -p packages

@@ -13,12 +12,18 @@ do
dpkg -x $pkg_name packages
done

export PATH=$PWD/packages/usr/local/bin:$PWD/packages/usr/bin:$PATH
for a in $archives
do
wget $a
(cd packages && tar xf ../$(basename $a))
done

export PATH=$PWD/packages/usr/local/llvm-or1k/bin:$PWD/packages/usr/local/bin:$PWD/packages/usr/bin:$PATH
export LD_LIBRARY_PATH=$PWD/packages/usr/lib/x86_64-linux-gnu:$PWD/packages/usr/local/x86_64-unknown-linux-gnu/or1k-elf/lib:$LD_LIBRARY_PATH

echo -e "export LD_LIBRARY_PATH=$LD_LIBRARY_PATH" >> $HOME/.mlabs/build_settings.sh
echo "export LD_LIBRARY_PATH=$LD_LIBRARY_PATH" >> $HOME/.mlabs/build_settings.sh
echo "export PATH=$PWD/packages/usr/local/llvm-or1k/bin:$PATH" >> $HOME/.mlabs/build_settings.sh

or1k-elf-as --version
or1k-elf-gcc --version
or1k-linux-as --version
llc --version
clang --version
llvm-as --version || true
13 changes: 9 additions & 4 deletions artiq/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,9 @@
from artiq.language.core import *
from artiq.language.experiment import Experiment
from artiq.language.db import *
from artiq.language.units import *
from artiq import language
from artiq.language import *
from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE,
PHASE_MODE_TRACKING)

__all__ = []
__all__.extend(language.__all__)
__all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE",
"PHASE_MODE_TRACKING"]
18 changes: 3 additions & 15 deletions artiq/coredevice/comm_dummy.py
Original file line number Diff line number Diff line change
@@ -1,21 +1,9 @@
from operator import itemgetter

from artiq.language.db import AutoDB
from artiq.language.units import ms
from artiq.coredevice.runtime import LinkInterface


class _RuntimeEnvironment(LinkInterface):
def __init__(self):
self.warmup_time = 1*ms

def emit_object(self):
return str(self.llvm_module)


class Comm(AutoDB):
def get_runtime_env(self):
return _RuntimeEnvironment()
class Comm:
def __init__(self, dmgr):
pass

def switch_clock(self, external):
pass
12 changes: 8 additions & 4 deletions artiq/coredevice/comm_generic.py
Original file line number Diff line number Diff line change
@@ -95,7 +95,12 @@ def _read_header(self):
def _write_header(self, length, ty):
self.open()
logger.debug("sending message: type=%r length=%d", ty, length)
self.write(struct.pack(">llB", 0x5a5a5a5a, length, ty.value))
self.write(struct.pack(">ll", 0x5a5a5a5a, length))
if ty is not None:
self.write(struct.pack("B", ty.value))

def reset_session(self):
self._write_header(0, None)

def check_ident(self):
self._write_header(9, _H2DMsgType.IDENT_REQUEST)
@@ -125,9 +130,8 @@ def load(self, kcode):
if ty != _D2HMsgType.LOAD_COMPLETED:
raise IOError("Incorrect reply from device: "+str(ty))

def run(self, kname, reset_now):
self._write_header(len(kname) + 10, _H2DMsgType.RUN_KERNEL)
self.write(struct.pack("B", reset_now))
def run(self, kname):
self._write_header(len(kname) + 9, _H2DMsgType.RUN_KERNEL)
self.write(bytes(kname, "ascii"))
logger.debug("running kernel: %s", kname)

9 changes: 4 additions & 5 deletions artiq/coredevice/comm_tcp.py
Original file line number Diff line number Diff line change
@@ -2,16 +2,15 @@
import socket

from artiq.coredevice.comm_generic import CommGeneric
from artiq.language.db import *


logger = logging.getLogger(__name__)


class Comm(CommGeneric, AutoDB):
class DBKeys:
host = Argument()
port = Argument(1381)
class Comm(CommGeneric):
def __init__(self, dmgr, host, port=1381):
self.host = host
self.port = port

def open(self):
if hasattr(self, "socket"):
27 changes: 12 additions & 15 deletions artiq/coredevice/core.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
import os

from artiq.language.core import *
from artiq.language.db import *
from artiq.language.units import ns

from artiq.transforms.inline import inline
@@ -14,7 +13,7 @@
from artiq.transforms.lower_time import lower_time
from artiq.transforms.unparse import unparse

from artiq.coredevice.runtime import Environment
from artiq.coredevice.runtime import Runtime

from artiq.py2llvm import get_runtime_binary

@@ -46,17 +45,16 @@ def _no_debug_unparse(label, node):
pass


class Core(AutoDB):
class DBKeys:
comm = Device()
ref_period = Argument(8*ns)
external_clock = Argument(False)
class Core:
def __init__(self, dmgr, ref_period=8*ns, external_clock=False):
self.comm = dmgr.get("comm")
self.ref_period = ref_period
self.external_clock = external_clock

def build(self):
self.first_run = True
self.core = self
self.comm.core = self
self.runtime_env = Environment()
self.runtime = Runtime()

def transform_stack(self, func_def, rpc_map, exception_map,
debug_unparse=_no_debug_unparse):
@@ -104,7 +102,7 @@ def compile(self, k_function, k_args, k_kwargs, with_attr_writeback=True):
debug_unparse("inline", func_def)
self.transform_stack(func_def, rpc_map, exception_map, debug_unparse)

binary = get_runtime_binary(self.runtime_env, func_def)
binary = get_runtime_binary(self.runtime, func_def)

return binary, rpc_map, exception_map

@@ -116,15 +114,14 @@ def run(self, k_function, k_args, k_kwargs):
binary, rpc_map, exception_map = self.compile(
k_function, k_args, k_kwargs)
self.comm.load(binary)
self.comm.run(k_function.__name__, self.first_run)
self.comm.run(k_function.__name__)
self.comm.serve(rpc_map, exception_map)
self.first_run = False

@kernel
def get_rtio_time(self):
return cycles_to_time(syscall("rtio_get_counter"))
def get_rtio_counter_mu(self):
return syscall("rtio_get_counter")

@kernel
def break_realtime(self):
t = syscall("rtio_get_counter") + 125000
at(cycles_to_time(t))
at_mu(syscall("rtio_get_counter") + 125000)
68 changes: 49 additions & 19 deletions artiq/coredevice/dds.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,4 @@
from artiq.language.core import *
from artiq.language.db import *
from artiq.language.units import *


@@ -23,21 +22,19 @@ def __exit__(self, type, value, traceback):
self.dds_bus.batch_exit()


class DDSBus(AutoDB):
class DDSBus:
"""Core device Direct Digital Synthesis (DDS) bus batching driver.
Manages batching of DDS commands on a DDS shared bus."""
class DBKeys:
core = Device()

def build(self):
def __init__(self, dmgr):
self.core = dmgr.get("core")
self.batch = _BatchContextManager(self)

@kernel
def batch_enter(self):
"""Starts a DDS command batch. All DDS commands are buffered
after this call, until ``batch_exit`` is called."""
syscall("dds_batch_enter", time_to_cycles(now()))
syscall("dds_batch_enter", now_mu())

@kernel
def batch_exit(self):
@@ -46,20 +43,21 @@ def batch_exit(self):
syscall("dds_batch_exit")


class DDS(AutoDB):
class _DDSGeneric:
"""Core device Direct Digital Synthesis (DDS) driver.
Controls one DDS channel managed directly by the core device's runtime.
This class should not be used directly, instead, use the chip-specific
drivers such as ``AD9858`` and ``AD9914``.
:param sysclk: DDS system frequency.
:param channel: channel number of the DDS device to control.
"""
class DBKeys:
core = Device()
sysclk = Argument()
channel = Argument()

def build(self):
def __init__(self, dmgr, sysclk, channel):
self.core = dmgr.get("core")
self.sysclk = sysclk
self.channel = channel
self.phase_mode = PHASE_MODE_CONTINUOUS

@portable
@@ -76,12 +74,24 @@ def ftw_to_frequency(self, ftw):
"""
return ftw*self.sysclk/2**32

@portable
def turns_to_pow(self, turns):
"""Returns the phase offset word corresponding to the given phase
in turns."""
return round(turns*2**self.pow_width)

@portable
def pow_to_turns(self, pow):
"""Returns the phase in turns corresponding to the given phase offset
word."""
return pow/2**self.pow_width

@kernel
def init(self):
"""Resets and initializes the DDS channel.
The runtime does this for all channels upon core device startup."""
syscall("dds_init", time_to_cycles(now()), self.channel)
syscall("dds_init", now_mu(), self.channel)

@kernel
def set_phase_mode(self, phase_mode):
@@ -104,17 +114,37 @@ def set_phase_mode(self, phase_mode):
self.phase_mode = phase_mode

@kernel
def set(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT):
def set_mu(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT):
"""Sets the DDS channel to the specified frequency and phase.
This uses machine units (FTW and POW). The frequency tuning word width
is 32, whereas the phase offset word width depends on the type of DDS
chip and can be retrieved via the ``pow_width`` attribute.
:param frequency: frequency to generate.
:param phase: adds an offset, in turns, to the phase.
:param phase_mode: if specified, overrides the default phase mode set
by ``set_phase_mode`` for this call.
"""
if phase_mode == _PHASE_MODE_DEFAULT:
phase_mode = self.phase_mode
syscall("dds_set", now_mu(), self.channel,
frequency, round(phase*2**self.pow_width), phase_mode)

@kernel
def set(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT):
"""Like ``set_mu``, but uses Hz and turns."""
self.set_mu(self.frequency_to_ftw(frequency),
self.turns_to_pow(phase), phase_mode)


class AD9858(_DDSGeneric):
"""Driver for AD9858 DDS chips. See ``_DDSGeneric`` for a description
of the functionality."""
pow_width = 14


syscall("dds_set", time_to_cycles(now()), self.channel,
self.frequency_to_ftw(frequency), round(phase*2**14),
phase_mode)
class AD9914(_DDSGeneric):
"""Driver for AD9914 DDS chips. See ``_DDSGeneric`` for a description
of the functionality."""
pow_width = 16
9 changes: 5 additions & 4 deletions artiq/coredevice/runtime.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
import os

import llvmlite.ir as ll
import llvmlite.binding as llvm
import llvmlite_or1k.ir as ll
import llvmlite_or1k.binding as llvm

from artiq.py2llvm import base_types, fractions, lists
from artiq.language import units
@@ -21,6 +21,7 @@
"ttl_set_oe": "Iib:n",
"ttl_set_sensitivity": "Iii:n",
"ttl_get": "iI:I",
"ttl_clock_set": "Iii:n",
"dds_init": "Ii:n",
"dds_batch_enter": "I:n",
"dds_batch_exit": "n:n",
@@ -195,7 +196,7 @@ def _debug_dump_obj(obj):
raise IOError


class Environment(LinkInterface):
class Runtime(LinkInterface):
def __init__(self):
self.cpu_type = "or1k"
# allow 1ms for all initial DDS programming
@@ -208,4 +209,4 @@ def emit_object(self):
return obj

def __repr__(self):
return "<Environment {}>".format(self.cpu_type)
return "<Runtime {}>".format(self.cpu_type)
Loading

0 comments on commit ac134bb

Please sign in to comment.