liteeth/phy: rename rgmii to s6rgmii since specific to Spartan6

enjoy-digital · enjoy-digital · commit 3cf46671e932 · 2015-08-05T10:33:08.000+02:00
Also remove autodetection support for RGMII. For it to work we would need to pass the device we are building for.
diff --git a/misoclib/com/liteeth/phy/__init__.py b/misoclib/com/liteeth/phy/__init__.py
@@ -17,9 +17,8 @@ def LiteEthPHY(clock_pads, pads, **kwargs):
             from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
             return LiteEthPHYGMII(clock_pads, pads, **kwargs)
     elif hasattr(pads, "rx_ctl"):
-         # This is a 10/100/1G RGMII PHY
-           from misoclib.com.liteeth.phy.rgmii import LiteEthPHYRGMII
-           return LiteEthPHYRGMII(clock_pads, pads, **kwargs)
+        # This is a 10/100/1G RGMII PHY
+        raise ValueError("RGMII PHYs are specific to vendors (for now), use direct instantiation")
     elif flen(pads.tx_data) == 4:
         # This is a MII PHY
         from misoclib.com.liteeth.phy.mii import LiteEthPHYMII
diff --git a/misoclib/com/liteeth/phy/s6rgmii.py b/misoclib/com/liteeth/phy/s6rgmii.py
@@ -1,3 +1,5 @@
+# RGMII PHY for Spartan-6
+
 from migen.genlib.io import DDROutput
 from migen.genlib.misc import WaitTimer
 from migen.genlib.fsm import FSM, NextState

Original file line number	Diff line number	Diff line change
`@@ -1,3 +1,5 @@`
	`1`	`+# RGMII PHY for Spartan-6`
	`2`	`+`
`1`	`3`	`from migen.genlib.io import DDROutput`
`2`	`4`	`from migen.genlib.misc import WaitTimer`
`3`	`5`	`from migen.genlib.fsm import FSM, NextState`