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pipistrello: smaller L2 cache
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sbourdeauducq committed Jun 18, 2015
1 parent 77ca8bb commit 3636025
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -71,7 +71,7 @@ class NIST_QC1(BaseSoC, AMPSoC):
def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type,
sdram_controller_settings=MiniconSettings(l2_size=128*1024),
sdram_controller_settings=MiniconSettings(l2_size=64*1024),
with_timer=False, **kwargs)
AMPSoC.__init__(self)
platform.toolchain.ise_commands += """

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