fhdl/specials: add Keep SynthesisDirective

enjoy-digital · enjoy-digital · commit d77a5fc5acff · 2015-06-23T16:14:42.000+02:00
diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
@@ -337,3 +337,8 @@ def emit_verilog(directive, ns, add_data_file):
         name_dict = dict((k, ns.get_name(sig)) for k, sig in directive.signals.items())
         formatted = directive.template.format(**name_dict)
         return "// synthesis " + formatted + "\n"
+
+
+class Keep(SynthesisDirective):
+    def __init__(self, signal):
+        SynthesisDirective.__init__(self, "attribute keep of {s} is true", s=signal)
