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liteeth/example_designs: use new Keep SynthesisDirective
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enjoy-digital committed Jun 23, 2015
1 parent 351e654 commit 125432b
Showing 1 changed file with 6 additions and 0 deletions.
6 changes: 6 additions & 0 deletions misoclib/com/liteeth/example_designs/targets/base.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from migen.bus import wishbone
from migen.bank.description import *
from migen.genlib.io import CRG
from migen.fhdl.specials import Keep
from mibuild.xilinx.vivado import XilinxVivadoToolchain

from misoclib.soc import SoC
@@ -45,6 +46,11 @@ def __init__(self, platform, clk_freq=166*1000000,
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)

if isinstance(platform.toolchain, XilinxVivadoToolchain):
self.specials += [
Keep(self.crg.cd_sys.clk),
Keep(self.phy.crg.cd_eth_rx.clk),
Keep(self.phy.crg.cd_eth_tx.clk)
]
platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]

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