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soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2…
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…_cache function when L2_SIZE is not defined
enjoy-digital committed Jun 19, 2015
1 parent 7c2d0fa commit f44956b
Showing 3 changed files with 7 additions and 8 deletions.
2 changes: 2 additions & 0 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -53,6 +53,8 @@ def register_sdram_phy(self, phy):
# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256*1024*1024)
l2_size = self.sdram_controller_settings.l2_size
if l2_size:
self.add_constant("L2_SIZE", l2_size)

# add a Wishbone interface to the DRAM
wb_sdram = wishbone.Interface()
3 changes: 3 additions & 0 deletions software/bios/main.c
Original file line number Diff line number Diff line change
@@ -355,7 +355,10 @@ static void do_command(char *c)
else if(strcmp(token, "mw") == 0) mw(get_token(&c), get_token(&c), get_token(&c));
else if(strcmp(token, "mc") == 0) mc(get_token(&c), get_token(&c), get_token(&c));
else if(strcmp(token, "crc") == 0) crc(get_token(&c), get_token(&c));

#ifdef L2_SIZE
else if(strcmp(token, "flushl2") == 0) flush_l2_cache();
#endif

#ifdef FLASH_BOOT_ADDRESS
else if(strcmp(token, "flashboot") == 0) flashboot();
10 changes: 2 additions & 8 deletions software/libbase/system.c
Original file line number Diff line number Diff line change
@@ -67,16 +67,14 @@ void flush_cpu_dcache(void)
#endif
}

#ifdef CSR_L2_CACHE_BASE
#ifdef L2_SIZE
void flush_l2_cache(void)
{
unsigned int l2_nwords;
unsigned int i;
register unsigned int addr;
register unsigned int dummy;

l2_nwords = 1 << l2_cache_size_read();
for(i=0;i<2*l2_nwords;i++) {
for(i=0;i<2*L2_SIZE;i++) {
addr = MAIN_RAM_BASE + i*4;
#if defined (__lm32__)
__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
@@ -87,8 +85,4 @@ void flush_l2_cache(void)
#endif
}
}
#else
void flush_l2_cache(void)
{
}
#endif

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