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bus/wishbone: remove size CSR from Cache (L2 size will be reported to…
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… the software as a constant)
enjoy-digital committed Jun 19, 2015
1 parent 7d8f4d1 commit 71627cf
Showing 1 changed file with 1 addition and 3 deletions.
4 changes: 1 addition & 3 deletions migen/bus/wishbone.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,6 @@
from migen.genlib.misc import split, displacer, optree, chooser
from migen.genlib.misc import FlipFlop, Counter
from migen.genlib.fsm import FSM, NextState
from migen.bank.description import *
from migen.bus.transactions import *

_layout = [
@@ -409,14 +408,13 @@ def __init__(self, master, slave):
Record.connect(master, slave)


class Cache(Module, AutoCSR):
class Cache(Module):
"""Cache
This module is a write-back wishbone cache that can be used as a L2 cache.
Cachesize (in 32-bit words) is the size of the data store and must be a power of 2
"""
def __init__(self, cachesize, master, slave):
self._size = CSRStatus(8, reset=log2_int(cachesize))
self.master = master
self.slave = slave

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