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base repository: m-labs/artiq
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base: 07a58dc0da63
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head repository: m-labs/artiq
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compare: ef96de7d2654
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Jun 21, 2015

  1. ad9858: make wb data 8 bit wide

    matches actual dds bus data width and saves bram
    jordens committed Jun 21, 2015
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    45ec5db View commit details
  2. Merge branch 'shrink-dds-wb'

    * shrink-dds-wb:
      ad9858: make wb data 8 bit wide
    jordens committed Jun 21, 2015
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    ef96de7 View commit details
Showing with 1 addition and 1 deletion.
  1. +1 −1 artiq/gateware/ad9858.py
2 changes: 1 addition & 1 deletion artiq/gateware/ad9858.py
Original file line number Diff line number Diff line change
@@ -38,7 +38,7 @@ def __init__(self, pads,
read_wait_cycles=10, hiz_wait_cycles=3,
bus=None):
if bus is None:
bus = wishbone.Interface()
bus = wishbone.Interface(data_width=8)
self.bus = bus

# # #