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pipistrello: fix FPGA speed grade
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fallen committed Jun 14, 2015
1 parent 33b536e commit 6e876c6
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion mibuild/platforms/pipistrello.py
Original file line number Diff line number Diff line change
@@ -130,7 +130,7 @@ class Platform(XilinxPlatform):
default_clk_period = 20

def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"

def create_programmer(self):

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