pipistrello: fix FPGA speed grade

fallen · fallen · commit 6e876c63ad58 · 2015-06-14T23:19:27.000+02:00
diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
@@ -130,7 +130,7 @@ class Platform(XilinxPlatform):
     default_clk_period = 20
 
     def __init__(self):
-        XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
+        XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
         self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"
 
     def create_programmer(self):
