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base repository: m-labs/misoc
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compare: 369cf4c4d769
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Jun 22, 2015

  1. liteeth/core/arp: fix missing MAC address in ARP reply

    @enjoy-digital
    enjoy-digital committed Jun 22, 2015
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    a3c0e5c View commit details

  2. liteeth/core/arp: fix table timer (wait_timer adaptation issue)

    @enjoy-digital
    enjoy-digital committed Jun 22, 2015
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    5c939b8 View commit details

  3. liteeth/example_designs: add false path between clock domains (speed … 

    …up implementation) and use automatic PHY detection
    @enjoy-digital
    enjoy-digital committed Jun 22, 2015
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    369cf4c View commit details
Showing with 19 additions and 7 deletions.
  1. +3 −3 misoclib/com/liteeth/core/arp/__init__.py
  2. +16 −4 misoclib/com/liteeth/example_designs/targets/base.py
6 changes: 3 additions & 3 deletions misoclib/com/liteeth/core/arp/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -185,6 +185,7 @@ def __init__(self, clk_freq, max_requests=8):
source.stb.eq(1),
source.reply.eq(1),
source.ip_address.eq(sink.ip_address),
source.mac_address.eq(sink.mac_address),
If(source.ack,
NextState("IDLE")
)
@@ -194,18 +195,17 @@ def __init__(self, clk_freq, max_requests=8):
update.eq(1),
NextState("CHECK_TABLE")
)
self.sync += [
self.sync += \
If(update,
cached_valid.eq(1),
cached_ip_address.eq(sink.ip_address),
cached_mac_address.eq(sink.mac_address),
).Else(
cached_timer.wait.eq(1),
If(cached_timer.done,
cached_valid.eq(0)
)
)
]
self.comb += cached_timer.wait.eq(~update)
found = Signal()
fsm.act("CHECK_TABLE",
If(cached_valid,
20 changes: 16 additions & 4 deletions misoclib/com/liteeth/example_designs/targets/base.py
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,7 @@
from migen.bus import wishbone
from migen.bank.description import *
from migen.genlib.io import CRG
from mibuild.xilinx.vivado import XilinxVivadoToolchain

from misoclib.soc import SoC
from misoclib.tools.litescope.common import *
@@ -10,14 +11,14 @@
from misoclib.com.uart.bridge import UARTWishboneBridge

from misoclib.com.liteeth.common import *
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
from misoclib.com.liteeth.phy import LiteEthPHY
from misoclib.com.liteeth.core import LiteEthUDPIPCore


class BaseSoC(SoC, AutoCSR):
csr_map = {
"phy": 11,
"core": 12
"phy": 11,
"core": 12
}
csr_map.update(SoC.csr_map)
def __init__(self, platform, clk_freq=166*1000000,
@@ -40,9 +41,20 @@ def __init__(self, platform, clk_freq=166*1000000,
self.add_wb_slave(lambda a: a[23:25] == 1, self.sram.bus)

# ethernet PHY and UDP/IP stack
self.submodules.phy = LiteEthPHYGMII(platform.request("eth_clocks"), platform.request("eth"))
self.submodules.phy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=clk_freq)
self.submodules.core = LiteEthUDPIPCore(self.phy, mac_address, convert_ip(ip_address), clk_freq)

if isinstance(platform.toolchain, XilinxVivadoToolchain):
platform.add_platform_command("""
create_clock -name sys_clk -period 6.0 [get_nets sys_clk]
create_clock -name eth_rx_clk -period 8.0 [get_nets eth_rx_clk]
create_clock -name eth_tx_clk -period 8.0 [get_nets eth_tx_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_rx_clk]
set_false_path -from [get_clocks eth_rx_clk] -to [get_clocks sys_clk]
set_false_path -from [get_clocks sys_clk] -to [get_clocks eth_tx_clk]
set_false_path -from [get_clocks eth_tx_clk] -to [get_clocks sys_clk]
""")


class BaseSoCDevel(BaseSoC, AutoCSR):
csr_map = {