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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: d25a07f66803
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Jun 18, 2015

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    38a0f63 View commit details
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Showing with 14 additions and 31 deletions.
  1. +3 −12 artiq/gateware/amp/kernel_cpu.py
  2. +3 −2 artiq/gateware/soc.py
  3. +0 −15 soc/runtime/mailbox.c
  4. +4 −1 soc/targets/artiq_kc705.py
  5. +4 −1 soc/targets/artiq_pipistrello.py
15 changes: 3 additions & 12 deletions artiq/gateware/amp/kernel_cpu.py
Original file line number Diff line number Diff line change
@@ -3,12 +3,11 @@
from migen.bus import wishbone

from misoclib.cpu import mor1kx
from misoclib.mem.sdram.frontend.wishbone2lasmi import WB2LASMI
from misoclib.soc import mem_decoder


class KernelCPU(Module):
def __init__(self, platform, lasmim,
def __init__(self, platform,
exec_address=0x40400000,
main_mem_origin=0x40000000,
l2_size=8192):
@@ -29,16 +28,8 @@ def __init__(self, platform, lasmim,
"sys_kernel")

# DRAM access
# XXX Vivado 2014.X workaround
from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE()(
WB2LASMI(l2_size//4, lasmim))
else:
self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
self.add_wb_slave(mem_decoder(main_mem_origin),
self.wishbone2lasmi.wishbone)
self.wb_sdram = wishbone.Interface()
self.add_wb_slave(mem_decoder(main_mem_origin), self.wb_sdram)

def get_csrs(self):
return [self._reset]
5 changes: 3 additions & 2 deletions artiq/gateware/soc.py
Original file line number Diff line number Diff line change
@@ -19,8 +19,9 @@ def __init__(self):

self.submodules.timer0 = timer.Timer(width=64)

self.submodules.kernel_cpu = amp.KernelCPU(
self.platform, self.sdram.crossbar.get_master())
self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
self.add_wb_sdram_if(self.kernel_cpu.wb_sdram)

self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i1)
15 changes: 0 additions & 15 deletions soc/runtime/mailbox.c
Original file line number Diff line number Diff line change
@@ -29,22 +29,8 @@ static void _flush_cpu_dcache(void)
mtspr(SPR_DCBIR, i);
}

/* TODO: do not use L2 cache in AMP systems */
static void _flush_l2_cache(void)
{
unsigned int i;
register unsigned int addr;
register unsigned int dummy;

for(i=0;i<2*8192/4;i++) {
addr = 0x40000000 + i*4;
__asm__ volatile("l.lwz %0, 0(%1)\n":"=r"(dummy):"r"(addr));
}
}

void mailbox_send(void *ptr)
{
_flush_l2_cache();
last_transmission = (unsigned int)ptr;
KERNELCPU_MAILBOX = last_transmission;
}
@@ -72,7 +58,6 @@ void *mailbox_receive(void)
return NULL;
else {
if(r) {
_flush_l2_cache();
_flush_cpu_dcache();
}
return (void *)r;
5 changes: 4 additions & 1 deletion soc/targets/artiq_kc705.py
Original file line number Diff line number Diff line change
@@ -6,6 +6,7 @@

from misoclib.com import gpio
from misoclib.soc import mem_decoder
from misoclib.mem.sdram.core.minicon import MiniconSettings
from targets.kc705 import MiniSoC

from artiq.gateware.soc import AMPSoC
@@ -48,7 +49,9 @@ class NIST_QC1(MiniSoC, AMPSoC):

def __init__(self, platform, cpu_type="or1k", **kwargs):
MiniSoC.__init__(self, platform,
cpu_type=cpu_type, with_timer=False, **kwargs)
cpu_type=cpu_type,
sdram_controller_settings=MiniconSettings(l2_size=128*1024),
with_timer=False, **kwargs)
AMPSoC.__init__(self)
platform.add_extension(nist_qc1.fmc_adapter_io)

5 changes: 4 additions & 1 deletion soc/targets/artiq_pipistrello.py
Original file line number Diff line number Diff line change
@@ -4,6 +4,7 @@

from misoclib.com import gpio
from misoclib.soc import mem_decoder
from misoclib.mem.sdram.core.minicon import MiniconSettings
from targets.pipistrello import BaseSoC

from artiq.gateware.soc import AMPSoC
@@ -69,7 +70,9 @@ class NIST_QC1(BaseSoC, AMPSoC):

def __init__(self, platform, cpu_type="or1k", **kwargs):
BaseSoC.__init__(self, platform,
cpu_type=cpu_type, with_timer=False, **kwargs)
cpu_type=cpu_type,
sdram_controller_settings=MiniconSettings(l2_size=128*1024),
with_timer=False, **kwargs)
AMPSoC.__init__(self)
platform.toolchain.ise_commands += """
trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf