soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, update comment...

enjoy-digital · enjoy-digital · commit 553262bcc14c · 2015-05-04T12:28:49.000+02:00
diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
@@ -59,8 +59,8 @@ def register_sdram_phy(self, phy):
 
             l2_size = self.sdram_controller_settings.l2_size
             if l2_size:
-                # XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
-                # Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
+                # XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
+                # Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
                 # Remove this workaround when fixed by Xilinx.
                 from mibuild.xilinx.vivado import XilinxVivadoToolchain
                 if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
