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soc/sdram: Vivado 2015.1 still does not fix issue with L2 cache, upda…
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enjoy-digital committed May 4, 2015
1 parent 438a085 commit 553262b
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -59,8 +59,8 @@ def register_sdram_phy(self, phy):

l2_size = self.sdram_controller_settings.l2_size
if l2_size:
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
# XXX Vivado ->2015.1 workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.2?).
# Remove this workaround when fixed by Xilinx.
from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):

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