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base repository: m-labs/misoc
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  • 3 commits
  • 24 files changed
  • 1 contributor

Commits on May 1, 2015

  1. liteusb: continue refactoring (virtual UART and DMA working on minisp…

    …artan6)
    
    - rename ft2232h phy to ft245.
    - make crc optional
    - fix depacketizer
    - refactor uart (it's now only a wrapper around standard UART)
    - fix and update dma
    enjoy-digital committed May 1, 2015
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    603b4cd View commit details
  2. liteusb: refactor software (use python instead of libftdicom in C) an…

    …d provide simple example.
    
    small modifications to fastftdi.c are also done to select our interface (A or B) and mode (synchronous, asynchronous)
    enjoy-digital committed May 1, 2015
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    da0fe2e View commit details
  3. Copy the full SHA
    23ba1cc View commit details
8 changes: 5 additions & 3 deletions misoclib/com/liteusb/common.py
Original file line number Diff line number Diff line change
@@ -3,6 +3,7 @@
from migen.actorlib.fifo import *
from migen.flow.actor import EndpointDescription
from migen.actorlib.packet import *
from migen.actorlib.structuring import Pipeline


packet_header_length = 9
@@ -49,11 +50,12 @@ def __init__(self, dw):


class LiteUSBSlavePort:
def __init__(self, dw):
def __init__(self, dw, tag):
self.sink = Sink(user_description(dw))
self.source = Source(user_description(dw))
self.tag = tag


class LiteUSBUserPort(LiteUSBSlavePort):
def __init__(self, dw):
LiteUSBSlavePort.__init__(self, dw)
def __init__(self, dw, tag):
LiteUSBSlavePort.__init__(self, dw, tag)
40 changes: 20 additions & 20 deletions misoclib/com/liteusb/core/__init__.py
Original file line number Diff line number Diff line change
@@ -3,29 +3,29 @@
from misoclib.com.liteusb.core.crc import LiteUSBCRC32Inserter, LiteUSBCRC32Checker
from misoclib.com.liteusb.core.crossbar import LiteUSBCrossbar

# XXX Header should be protected by CRC

class LiteUSBCore(Module):
def __init__(self, phy):
def __init__(self, phy, clk_freq, with_crc=True):
rx_pipeline = [phy]
tx_pipeline = [phy]

# depacketizer / packetizer
self.submodules.depacketizer = LiteUSBDepacketizer()
self.submodules.depacketizer = LiteUSBDepacketizer(clk_freq)
self.submodules.packetizer = LiteUSBPacketizer()
self.comb += [
Record.connect(phy.source, self.depacketizer.sink),
Record.connect(self.packetizer.source, phy.sink)
]
rx_pipeline += [self.depacketizer]
tx_pipeline += [self.packetizer]

# crc checker / inserter
self.submodules.crc_rx = LiteUSBCRC32Checker()
self.submodules.crc_tx = LiteUSBCRC32Inserter()
self.comb += [
Record.connect(self.depacketizer.source, self.crc_rx.sink),
Record.connect(self.crc_tx.source, self.packetizer.sink)
]
if with_crc:
# crc checker / inserter
self.submodules.crc_rx = LiteUSBCRC32Checker()
self.submodules.crc_tx = LiteUSBCRC32Inserter()
rx_pipeline += [self.crc_rx]
tx_pipeline += [self.crc_tx]

# crossbar
# crossbar
self.submodules.crossbar = LiteUSBCrossbar()
self.comb += [
Record.connect(self.crossbar.master.source, self.crc_tx.sink),
Record.connect(self.crc_rx.source, self.crossbar.master.sink)
]
rx_pipeline += [self.crossbar.master]
tx_pipeline += [self.crossbar.master]

# graph
self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
self.submodules.tx_pipeline = Pipeline(*reversed(tx_pipeline))
2 changes: 1 addition & 1 deletion misoclib/com/liteusb/core/crossbar.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@ def __init__(self):
self.dispatch_param = "dst"

def get_port(self, dst):
port = LiteUSBUserPort(8)
port = LiteUSBUserPort(8, dst)
if dst in self.users.keys():
raise ValueError("Destination {0:#x} already assigned".format(dst))
self.users[dst] = port
6 changes: 3 additions & 3 deletions misoclib/com/liteusb/core/packet.py
Original file line number Diff line number Diff line change
@@ -66,7 +66,7 @@ def __init__(self):


class LiteUSBDepacketizer(Module):
def __init__(self, timeout=10):
def __init__(self, clk_freq, timeout=10):
self.sink = sink = Sink(phy_description(8))
self.source = source = Source(user_description(8))

@@ -116,9 +116,9 @@ def __init__(self, timeout=10):
header_pack.source.ack.eq(1),
)

self.submodules.timeout = Timeout(60000000*timeout) #XXX use clk_freq
self.submodules.timeout = Timeout(clk_freq*timeout)
self.comb += [
self.timeout.reset.eq(fsm.ongoing("WAIT_SOP")),
self.timeout.reset.eq(fsm.ongoing("IDLE")),
self.timeout.ce.eq(1)
]

19 changes: 9 additions & 10 deletions misoclib/com/liteusb/frontend/dma.py
Original file line number Diff line number Diff line change
@@ -16,7 +16,7 @@ def __init__(self, lasmim):

# Pack data
pack_factor = lasmim.dw//8
pack = structuring.Pack(phy_layout, pack_factor, reverse=True)
pack = structuring.Pack(phy_description(8), pack_factor, reverse=True)
cast = structuring.Cast(pack.source.payload.layout, lasmim.dw)

# DMA
@@ -61,12 +61,12 @@ def __init__(self, lasmim, tag):
pack_factor = lasmim.dw//8
packed_dat = structuring.pack_layout(8, pack_factor)
cast = structuring.Cast(lasmim.dw, packed_dat)
unpack = structuring.Unpack(pack_factor, phy_layout, reverse=True)
unpack = structuring.Unpack(pack_factor, phy_description(8), reverse=True)

# Graph
cnt = Signal(32)
self.sync += \
If(self.dma.generator._r_shoot.re,
If(self.dma.generator._shoot.re,
cnt.eq(0)
).Elif(source.stb & source.ack,
cnt.eq(cnt + 1)
@@ -92,12 +92,11 @@ def __init__(self, lasmim, tag):


class LiteUSBDMA(Module, AutoCSR):
def __init__(self, lasmim_dma_wr, lasmim_dma_rd, tag):
self.tag = tag

def __init__(self, port, lasmim_dma_wr, lasmim_dma_rd):
self.submodules.writer = LiteUSBDMAWriter(lasmim_dma_wr)
self.submodules.reader = LiteUSBDMAReader(lasmim_dma_rd, self.tag)
self.submodules.reader = LiteUSBDMAReader(lasmim_dma_rd, port.tag)
self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)

self.sink = self.writer.sink
self.source = self.reader.source
self.comb += [
Record.connect(port.source, self.writer.sink),
Record.connect(self.reader.source, port.sink),
]
66 changes: 21 additions & 45 deletions misoclib/com/liteusb/frontend/uart.py
Original file line number Diff line number Diff line change
@@ -1,59 +1,35 @@
from migen.fhdl.std import *
from migen.bank.description import *
from migen.bank.eventmanager import *
from migen.actorlib.fifo import SyncFIFO

from misoclib.com.liteusb.common import *
from misoclib.com.uart import UART

class LiteUSBUARTPHY:
def __init__(self):
self.sink = Sink([("data", 8)])
self.source = Source([("data", 8)])

class LiteUSBUART(Module, AutoCSR):
def __init__(self, tag, fifo_depth=64):
self.tag = tag
class LiteUSBUART(UART):
def __init__(self, port,
tx_fifo_depth=16,
rx_fifo_depth=16):

self._rxtx = CSR(8)

self.submodules.ev = EventManager()
self.ev.tx = EventSourcePulse()
self.ev.rx = EventSourceLevel()
self.ev.finalize()

self.source = source = Source(user_description(8))
self.sink = sink = Sink(user_description(8))

# # #
phy = LiteUSBUARTPHY()
UART.__init__(self, phy, tx_fifo_depth, rx_fifo_depth)

# TX
tx_start = self._rxtx.re
tx_done = self.ev.tx.trigger

self.sync += \
If(tx_start,
source.stb.eq(1),
source.data.eq(self._rxtx.r),
).Elif(tx_done,
source.stb.eq(0)
)

self.comb += [
source.sop.eq(1),
source.eop.eq(1),
source.length.eq(1),
source.dst.eq(self.tag),
tx_done.eq(source.stb & source.ack),
port.sink.stb.eq(phy.sink.stb),
port.sink.sop.eq(1),
port.sink.eop.eq(1),
port.sink.length.eq(1),
port.sink.dst.eq(port.tag),
port.sink.data.eq(phy.sink.data),
phy.sink.ack.eq(port.sink.ack)
]

# RX
rx_available = self.ev.rx.trigger

rx_fifo = SyncFIFO(8, fifo_depth)
self.submodules += rx_fifo
self.comb += [
Record.connect(sink, rx_fifo.sink),

rx_fifo.we.eq(sink.stb),
sink.ack.eq(sink.stb & rx_fifo.writable),
rx_fifo.din.eq(sink.data),
rx_available.eq(rx_fifo.stb),
rx_fifo.ack.eq(self.ev.rx.clear),
self._rxtx.w.eq(rx_fifo.dout)
phy.source.stb.eq(port.source.stb),
phy.source.data.eq(port.source.data),
port.source.ack.eq(phy.source.ack)
]
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