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soc: factor timer, kernel CPU and mailbox
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from misoclib.soc import mem_decoder | ||
from misoclib.cpu.peripherals import timer | ||
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from artiq.gateware import amp | ||
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class AMPSoC: | ||
"""Contains timer, kernel CPU and mailbox for ARTIQ SoCs. | ||
Users must disable the timer from the platform SoC and provide | ||
a "mailbox" entry in the memory map. | ||
""" | ||
def __init__(self): | ||
if not hasattr(self, "cpu_or_bridge"): | ||
raise ValueError("Platform SoC must be initialized first") | ||
if hasattr(self, "timer0"): | ||
raise ValueError("Timer already exists. " | ||
"Initialize platform SoC using with_timer=False") | ||
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self.submodules.timer0 = timer.Timer(width=64) | ||
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self.submodules.kernel_cpu = amp.KernelCPU( | ||
self.platform, self.sdram.crossbar.get_master()) | ||
self.submodules.mailbox = amp.Mailbox() | ||
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), | ||
self.mailbox.i1) | ||
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), | ||
self.mailbox.i2) | ||
self.add_memory_region("mailbox", | ||
self.mem_map["mailbox"] | 0x80000000, 4) |
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