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sbourdeauducqsbourdeauducq
committedMay 1, 2015
soc: factor timer, kernel CPU and mailbox
·
8.00.1
1 parent 1684586 commit 62669f9

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4 files changed

+48
-37
lines changed

4 files changed

+48
-37
lines changed
 

Diff for: ‎artiq/frontend/artiq_flash.sh

+2-2
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ fi
9090
if [ "$BOARD" == "kc705" ]
9191
then
9292
UDEV_RULES=99-kc705.rules
93-
BITSTREAM=artiq_kc705-top-kc705.bit
93+
BITSTREAM=artiq_kc705-nist_qc1-kc705.bit
9494
CABLE=jtaghs1_fast
9595
PROXY=bscan_spi_kc705.bit
9696
BIOS_ADDR=0xaf0000
@@ -100,7 +100,7 @@ then
100100
elif [ "$BOARD" == "pipistrello" ]
101101
then
102102
UDEV_RULES=99-papilio.rules
103-
BITSTREAM=artiq_pipistrello-top-pipistrello.bin
103+
BITSTREAM=artiq_pipistrello-nist_qc1-pipistrello.bin
104104
CABLE=papilio
105105
PROXY=bscan_spi_lx45_csg324.bit
106106
BIOS_ADDR=0x170000

Diff for: ‎artiq/gateware/soc.py

+30
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
from misoclib.soc import mem_decoder
2+
from misoclib.cpu.peripherals import timer
3+
4+
from artiq.gateware import amp
5+
6+
7+
class AMPSoC:
8+
"""Contains timer, kernel CPU and mailbox for ARTIQ SoCs.
9+
10+
Users must disable the timer from the platform SoC and provide
11+
a "mailbox" entry in the memory map.
12+
"""
13+
def __init__(self):
14+
if not hasattr(self, "cpu_or_bridge"):
15+
raise ValueError("Platform SoC must be initialized first")
16+
if hasattr(self, "timer0"):
17+
raise ValueError("Timer already exists. "
18+
"Initialize platform SoC using with_timer=False")
19+
20+
self.submodules.timer0 = timer.Timer(width=64)
21+
22+
self.submodules.kernel_cpu = amp.KernelCPU(
23+
self.platform, self.sdram.crossbar.get_master())
24+
self.submodules.mailbox = amp.Mailbox()
25+
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
26+
self.mailbox.i1)
27+
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
28+
self.mailbox.i2)
29+
self.add_memory_region("mailbox",
30+
self.mem_map["mailbox"] | 0x80000000, 4)

Diff for: ‎soc/targets/artiq_kc705.py

+8-17
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,8 @@
99
from misoclib.cpu.peripherals import timer
1010
from targets.kc705 import MiniSoC
1111

12-
from artiq.gateware import amp, rtio, ad9858, nist_qc1
12+
from artiq.gateware.soc import AMPSoC
13+
from artiq.gateware import rtio, ad9858, nist_qc1
1314
from artiq.gateware.rtio.phy import ttl_simple
1415

1516

@@ -31,7 +32,7 @@ def __init__(self, platform, rtio_internal_clk):
3132
o_O=self.cd_rtio.clk)
3233

3334

34-
class Top(MiniSoC):
35+
class NIST_QC1(MiniSoC, AMPSoC):
3536
csr_map = {
3637
"rtio": None, # mapped on Wishbone instead
3738
"rtiocrg": 13,
@@ -48,7 +49,7 @@ class Top(MiniSoC):
4849
def __init__(self, platform, cpu_type="or1k", **kwargs):
4950
MiniSoC.__init__(self, platform,
5051
cpu_type=cpu_type, with_timer=False, **kwargs)
51-
self.submodules.timer0 = timer.Timer(width=64)
52+
AMPSoC.__init__(self)
5253
platform.add_extension(nist_qc1.fmc_adapter_io)
5354

5455
self.submodules.leds = gpio.GPIOOut(Cat(
@@ -98,27 +99,17 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
9899
set_false_path -from [get_clocks rio_clk] -to [get_clocks rsys_clk]
99100
""", rsys_clk=self.rtio.cd_rsys.clk, rio_clk=self.rtio.cd_rio.clk)
100101

101-
# Kernel CPU
102-
self.submodules.kernel_cpu = amp.KernelCPU(
103-
platform, self.sdram.crossbar.get_master())
104-
self.submodules.mailbox = amp.Mailbox()
105-
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
106-
self.mailbox.i1)
107-
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
108-
self.mailbox.i2)
109-
self.add_memory_region("mailbox",
110-
self.mem_map["mailbox"] + 0x80000000, 4)
111-
102+
# CPU connections
112103
rtio_csrs = self.rtio.get_csrs()
113104
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
114105
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
115106
self.rtiowb.bus)
116-
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
107+
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
117108
rtio_csrs)
118109

119110
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
120111
self.dds.bus)
121-
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
112+
self.add_memory_region("dds", self.mem_map["dds"] | 0x80000000, 64*4)
122113

123114

124-
default_subtarget = Top
115+
default_subtarget = NIST_QC1

Diff for: ‎soc/targets/artiq_pipistrello.py

+8-18
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44

55
from misoclib.com import gpio
66
from misoclib.soc import mem_decoder
7-
from misoclib.cpu.peripherals import timer
87
from targets.pipistrello import BaseSoC
98

10-
from artiq.gateware import amp, rtio, ad9858, nist_qc1
9+
from artiq.gateware.soc import AMPSoC
10+
from artiq.gateware import rtio, ad9858, nist_qc1
1111
from artiq.gateware.rtio.phy import ttl_simple
1212

1313

@@ -52,7 +52,7 @@ def __init__(self, platform):
5252
""", int_clk=rtio_internal_clk, ext_clk=rtio_external_clk)
5353

5454

55-
class Top(BaseSoC):
55+
class NIST_QC1(BaseSoC, AMPSoC):
5656
csr_map = {
5757
"rtio": None, # mapped on Wishbone instead
5858
"rtiocrg": 13,
@@ -69,7 +69,7 @@ class Top(BaseSoC):
6969
def __init__(self, platform, cpu_type="or1k", **kwargs):
7070
BaseSoC.__init__(self, platform,
7171
cpu_type=cpu_type, with_timer=False, **kwargs)
72-
self.submodules.timer0 = timer.Timer(width=64)
72+
AMPSoC.__init__(self)
7373
platform.toolchain.ise_commands += """
7474
trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd {build_name}.pcf
7575
"""
@@ -125,27 +125,17 @@ def __init__(self, platform, cpu_type="or1k", **kwargs):
125125
self.submodules.dds = ad9858.AD9858(dds_pads)
126126
self.comb += dds_pads.fud_n.eq(~fud)
127127

128-
# Kernel CPU
129-
self.submodules.kernel_cpu = amp.KernelCPU(
130-
platform, self.sdram.crossbar.get_master())
131-
self.submodules.mailbox = amp.Mailbox()
132-
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
133-
self.mailbox.i1)
134-
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
135-
self.mailbox.i2)
136-
self.add_memory_region("mailbox",
137-
self.mem_map["mailbox"] + 0x80000000, 4)
138-
128+
# CPU connections
139129
rtio_csrs = self.rtio.get_csrs()
140130
self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
141131
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
142132
self.rtiowb.bus)
143-
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
133+
self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
144134
rtio_csrs)
145135

146136
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
147137
self.dds.bus)
148-
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
138+
self.add_memory_region("dds", self.mem_map["dds"] | 0x80000000, 64*4)
149139

150140

151-
default_subtarget = Top
141+
default_subtarget = NIST_QC1

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