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enjoy-digitalenjoy-digital
committedMay 2, 2015
liteusb: add simple example design with wishbone bridge and software to control it
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0.120.1
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Diff for: ‎misoclib/com/liteusb/README

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Copyright 2015 / EnjoyDigital / M-Labs Ltd
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8-
A small footprint and configurable USB core
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A small footprint and configurable USB core
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powered by Migen
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[> Doc

Diff for: ‎misoclib/com/liteusb/example_designs/build/.keep_me

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Diff for: ‎misoclib/com/liteusb/example_designs/make.py

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#!/usr/bin/env python3
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import sys
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import os
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import argparse
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import subprocess
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import struct
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import importlib
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from mibuild.tools import write_to_file
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from migen.util.misc import autotype
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from migen.fhdl import verilog, edif
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from migen.fhdl.structure import _Fragment
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from migen.bank.description import CSRStatus
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from mibuild import tools
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from mibuild.xilinx.common import *
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from misoclib.soc import cpuif
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#from misoclib.lit.liteusb.common import *
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def _import(default, name):
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return importlib.import_module(default + "." + name)
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def _get_args():
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parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
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description="""\
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LiteUSB - based on Migen.
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This program builds and/or loads LiteUSB components.
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One or several actions can be specified:
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clean delete previous build(s).
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build-rtl build verilog rtl.
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build-bitstream build-bitstream build FPGA bitstream.
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build-csr-csv save CSR map into CSV file.
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load-bitstream load bitstream into volatile storage.
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all clean, build-csr-csv, build-bitstream, load-bitstream.
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""")
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parser.add_argument("-t", "--target", default="simple", help="Core type to build")
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parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
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parser.add_argument("-p", "--platform", default=None, help="platform to build for")
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parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
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parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
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parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
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parser.add_argument("action", nargs="+", help="specify an action")
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return parser.parse_args()
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# Note: misoclib need to be installed as a python library
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if __name__ == "__main__":
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args = _get_args()
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# create top-level Core object
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target_module = _import("targets", args.target)
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if args.sub_target:
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top_class = getattr(target_module, args.sub_target)
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else:
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top_class = target_module.default_subtarget
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if args.platform is None:
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if hasattr(top_class, "default_platform"):
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platform_name = top_class.default_platform
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else:
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raise ValueError("Target has no default platform, specify a platform with -p your_platform")
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else:
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platform_name = args.platform
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platform_module = _import("mibuild.platforms", platform_name)
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platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
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platform = platform_module.Platform(**platform_kwargs)
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build_name = top_class.__name__.lower() + "-" + platform_name
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top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
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soc = top_class(platform, **top_kwargs)
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soc.finalize()
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memory_regions = soc.get_memory_regions()
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csr_regions = soc.get_csr_regions()
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# decode actions
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action_list = ["clean", "build-csr-csv", "build-bitstream", "load-bitstream", "all"]
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actions = {k: False for k in action_list}
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for action in args.action:
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if action in actions:
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actions[action] = True
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else:
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print("Unknown action: "+action+". Valid actions are:")
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for a in action_list:
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print(" "+a)
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sys.exit(1)
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print("""
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__ _ __ __ _________
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/ / (_) /____ / / / / __/ _ )
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/ /__/ / __/ -_) /_/ /\ \/ _ |
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/____/_/\__/\__/\____/___/____/
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A small footprint and configurable USB core
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powered by Migen
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====== Building parameters: ======
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System Clk: {} MHz
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===============================""".format(
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soc.clk_freq/1000000))
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# dependencies
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if actions["all"]:
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actions["build-csr-csv"] = True
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actions["build-bitstream"] = True
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actions["load-bitstream"] = True
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if actions["build-bitstream"]:
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actions["build-csr-csv"] = True
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actions["build-bitstream"] = True
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actions["load-bitstream"] = True
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if actions["clean"]:
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subprocess.call(["rm", "-rf", "build/*"])
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if actions["build-csr-csv"]:
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csr_csv = cpuif.get_csr_csv(csr_regions)
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write_to_file(args.csr_csv, csr_csv)
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if actions["build-bitstream"]:
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vns = platform.build(soc, build_name=build_name, run=True)
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if hasattr(soc, "do_exit") and vns is not None:
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if hasattr(soc.do_exit, '__call__'):
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soc.do_exit(vns)
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if actions["load-bitstream"]:
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prog = platform.create_programmer()
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prog.load_bitstream("build/" + build_name + platform.bitstream_ext)

Diff for: ‎misoclib/com/liteusb/example_designs/targets/__init__.py

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Diff for: ‎misoclib/com/liteusb/example_designs/targets/simple.py

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from migen.bank.description import *
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from migen.genlib.io import CRG
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from migen.actorlib.fifo import SyncFIFO
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from misoclib.soc import SoC
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from misoclib.com.liteusb.common import *
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from misoclib.com.liteusb.phy.ft245 import FT245PHY
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from misoclib.com.liteusb.core import LiteUSBCore
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from misoclib.com.liteusb.frontend.wishbone import LiteUSBWishboneBridge
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from misoclib.com.gpio import GPIOOut
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class LiteUSBSoC(SoC, AutoCSR):
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csr_map = {}
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csr_map.update(SoC.csr_map)
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usb_map = {
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"bridge": 0
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}
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def __init__(self, platform):
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clk_freq = int((1/(platform.default_clk_period))*1000000000)
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SoC.__init__(self, platform, clk_freq,
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cpu_type="none",
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with_csr=True, csr_data_width=32,
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with_uart=False,
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with_identifier=True,
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with_timer=False
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)
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self.submodules.crg = CRG(platform.request(platform.default_clk_name))
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self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
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self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
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# Wishbone Bridge
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usb_bridge_port = self.usb_core.crossbar.get_port(self.usb_map["bridge"])
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self.add_cpu_or_bridge(LiteUSBWishboneBridge(usb_bridge_port, self.clk_freq))
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self.add_wb_master(self.cpu_or_bridge.wishbone)
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# Leds
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leds = Cat(iter([platform.request("user_led", i) for i in range(8)]))
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self.submodules.leds = GPIOOut(leds)
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default_subtarget = LiteUSBSoC

Diff for: ‎misoclib/com/liteusb/example_designs/test/Makefile

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LITEUSBDIR=../../software
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dll:
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cd $(LITEUSBDIR)/ftdi/windows && make all
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cp $(LITEUSBDIR)/ftdi/libftdicom.dll libftdicom.dll
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clean:
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rm -f libftdicom.dll

Diff for: ‎misoclib/com/liteusb/example_designs/test/make.py

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#!/usr/bin/env python3
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import argparse
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import importlib
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FTDI_INTERFACE_A = 1
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FTDI_INTERFACE_B = 2
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def _get_args():
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parser = argparse.ArgumentParser()
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parser.add_argument("--tag", default=0, help="USB channel tag")
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parser.add_argument("--busword", default=32, help="CSR busword")
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parser.add_argument("test", nargs="+", help="specify a test")
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return parser.parse_args()
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if __name__ == "__main__":
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args = _get_args()
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from misoclib.com.liteusb.software.wishbone import LiteUSBWishboneDriver
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wb = LiteUSBWishboneDriver("ft2232h", FTDI_INTERFACE_B, "asynchronous",
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tag=int(args.tag),
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busword=int(args.busword),
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addrmap="./csr.csv",
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debug=False)
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def _import(name):
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return importlib.import_module(name)
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for test in args.test:
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t = _import(test)
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t.main(wb)

Diff for: ‎misoclib/com/liteusb/example_designs/test/test_regs.py

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def main(wb):
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wb.open()
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regs = wb.regs
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# # #
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for i in range(64):
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wb.regs.leds_out.write(i)
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print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
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print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
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print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
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# # #
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wb.close()

Diff for: ‎misoclib/com/liteusb/frontend/__init__.py

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Diff for: ‎misoclib/com/liteusb/software/wishbone.py

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from misoclib.tools.litescope.software.driver.reg import *
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from misoclib.com.liteusb.software.ftdi import FTDIComDevice
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class LiteUSBWishboneDriverFTDI:

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