m-labs · May 2, 2015 · May 2, 2015 · May 2, 2015 · May 2, 2015 · May 2, 2015
diff --git a/misoclib/com/gpio/__init__.py → misoclib/com/gpio.py b/misoclib/com/gpio/__init__.py → misoclib/com/gpio.py
diff --git a/misoclib/com/liteeth/core/__init__.py b/misoclib/com/liteeth/core/__init__.py
@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 from misoclib.com.liteeth.core.arp import LiteEthARP
 from misoclib.com.liteeth.core.ip import LiteEthIP
 from misoclib.com.liteeth.core.udp import LiteEthUDP

diff --git a/misoclib/com/liteeth/mac/__init__.py → misoclib/com/liteeth/core/mac/__init__.py b/misoclib/com/liteeth/mac/__init__.py → misoclib/com/liteeth/core/mac/__init__.py
@@ -1,12 +1,14 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.common import *
-from misoclib.com.liteeth.mac.core import LiteEthMACCore
-from misoclib.com.liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
+from misoclib.com.liteeth.core.mac.common import *
+from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
+from misoclib.com.liteeth.core.mac.frontend.wishbone import LiteEthMACWishboneInterface
 
 
 class LiteEthMAC(Module, AutoCSR):
-    def __init__(self, phy, dw, interface="crossbar", endianness="big",
-            with_preamble_crc=True):
+    def __init__(self, phy, dw,
+                 interface="crossbar",
+                 endianness="big",
+                 with_preamble_crc=True):
         self.submodules.core = LiteEthMACCore(phy, dw, endianness, with_preamble_crc)
         self.csrs = []
         if interface == "crossbar":
@@ -24,10 +26,8 @@ def __init__(self, phy, dw, interface="crossbar", endianness="big",
             self.comb += Port.connect(self.interface, self.core)
             self.ev, self.bus = self.interface.sram.ev, self.interface.bus
             self.csrs = self.interface.get_csrs() + self.core.get_csrs()
-        elif interface == "dma":
-            raise NotImplementedError
         else:
-            raise ValueError(interface + " not supported by LiteEthMac!")
+            raise NotImplementedError
 
     def get_csrs(self):
         return self.csrs
diff --git a/misoclib/com/liteeth/mac/common.py → misoclib/com/liteeth/core/mac/common.py b/misoclib/com/liteeth/mac/common.py → misoclib/com/liteeth/core/mac/common.py
diff --git a/misoclib/com/liteeth/mac/core/__init__.py → ...lib/com/liteeth/core/mac/core/__init__.py b/misoclib/com/liteeth/mac/core/__init__.py → ...lib/com/liteeth/core/mac/core/__init__.py
@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
+from misoclib.com.liteeth.core.mac.core import gap, preamble, crc, padding, last_be
 from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
 
 

diff --git a/misoclib/com/liteeth/mac/core/crc.py → misoclib/com/liteeth/core/mac/core/crc.py b/misoclib/com/liteeth/mac/core/crc.py → misoclib/com/liteeth/core/mac/core/crc.py
diff --git a/misoclib/com/liteeth/mac/core/gap.py → misoclib/com/liteeth/core/mac/core/gap.py b/misoclib/com/liteeth/mac/core/gap.py → misoclib/com/liteeth/core/mac/core/gap.py
diff --git a/misoclib/com/liteeth/mac/core/last_be.py → ...clib/com/liteeth/core/mac/core/last_be.py b/misoclib/com/liteeth/mac/core/last_be.py → ...clib/com/liteeth/core/mac/core/last_be.py
diff --git a/misoclib/com/liteeth/mac/core/padding.py → ...clib/com/liteeth/core/mac/core/padding.py b/misoclib/com/liteeth/mac/core/padding.py → ...clib/com/liteeth/core/mac/core/padding.py
diff --git a/misoclib/com/liteeth/mac/core/preamble.py → ...lib/com/liteeth/core/mac/core/preamble.py b/misoclib/com/liteeth/mac/core/preamble.py → ...lib/com/liteeth/core/mac/core/preamble.py
diff --git a/...clib/com/liteeth/mac/frontend/__init__.py → ...com/liteeth/core/mac/frontend/__init__.py b/...clib/com/liteeth/mac/frontend/__init__.py → ...com/liteeth/core/mac/frontend/__init__.py
diff --git a/misoclib/com/liteeth/mac/frontend/sram.py → ...lib/com/liteeth/core/mac/frontend/sram.py b/misoclib/com/liteeth/mac/frontend/sram.py → ...lib/com/liteeth/core/mac/frontend/sram.py
diff --git a/...clib/com/liteeth/mac/frontend/wishbone.py → ...com/liteeth/core/mac/frontend/wishbone.py b/...clib/com/liteeth/mac/frontend/wishbone.py → ...com/liteeth/core/mac/frontend/wishbone.py
@@ -1,5 +1,5 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.frontend import sram
+from misoclib.com.liteeth.core.mac.frontend import sram
 
 from migen.bus import wishbone
 from migen.fhdl.simplify import FullMemoryWE

diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py
@@ -4,10 +4,11 @@
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
 from misoclib.tools.litescope.frontend.la import LiteScopeLA
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
+from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
+
 from misoclib.com.liteeth.common import *
 from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
 from misoclib.com.liteeth.core import LiteEthUDPIPCore
@@ -30,7 +31,7 @@ def __init__(self, platform, clk_freq=166*1000000,
             with_identifier=True,
             with_timer=False
         )
-        self.add_cpu_or_bridge(LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200))
+        self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 

diff --git a/misoclib/com/liteeth/example_designs/targets/tty.py b/misoclib/com/liteeth/example_designs/targets/tty.py
@@ -3,7 +3,6 @@
 from misoclib.tools.litescope.core.port import LiteScopeTerm
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.generic import *
 
 from targets.base import BaseSoC
 from misoclib.com.liteeth.frontend.tty import LiteEthTTY

diff --git a/misoclib/com/liteeth/example_designs/test/make.py b/misoclib/com/liteeth/example_designs/test/make.py
@@ -19,12 +19,12 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.software.driver.uart import LiteScopeUART2WishboneDriver
+        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
-        from misoclib.tools.litescope.software.driver.etherbone import LiteScopeEtherboneDriver
-        wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
+        from misoclib.com.liteeth.software.wishbone import LiteETHWishboneBridgeDriver
+        wb = LiteETHWishboneBridgeDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
     else:
         ValueError("Invalid bridge {}".format(args.bridge))
 

diff --git a/misoclib/com/liteeth/frontend/etherbone/__init__.py b/misoclib/com/liteeth/frontend/etherbone/__init__.py
@@ -1,8 +1,8 @@
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.core.etherbone.packet import *
-from misoclib.com.liteeth.core.etherbone.probe import *
-from misoclib.com.liteeth.core.etherbone.record import *
-from misoclib.com.liteeth.core.etherbone.wishbone import *
+from misoclib.com.liteeth.frontend.etherbone.packet import *
+from misoclib.com.liteeth.frontend.etherbone.probe import *
+from misoclib.com.liteeth.frontend.etherbone.record import *
+from misoclib.com.liteeth.frontend.etherbone.wishbone import *
 
 
 class LiteEthEtherbone(Module):

diff --git a/...clib/com/liteeth/frontend/tty/__init__.py → misoclib/com/liteeth/frontend/tty.py b/...clib/com/liteeth/frontend/tty/__init__.py → misoclib/com/liteeth/frontend/tty.py
diff --git a/.../com/litepcie/frontend/bridge/__init__.py → misoclib/com/liteeth/software/__init__.py b/.../com/litepcie/frontend/bridge/__init__.py → misoclib/com/liteeth/software/__init__.py
diff --git a/...ls/litescope/software/driver/etherbone.py → misoclib/com/liteeth/software/wishbone.py b/...ls/litescope/software/driver/etherbone.py → misoclib/com/liteeth/software/wishbone.py
@@ -1,10 +1,11 @@
 import socket
+
 from misoclib.tools.litescope.software.driver.reg import *
 
 from liteeth.test.model.etherbone import *
 
 
-class LiteScopeEtherboneDriver:
+class LiteEthWishboneDriver:
     def __init__(self, ip_address, udp_port=20000, addrmap=None, busword=8, debug=False):
         self.ip_address = ip_address
         self.udp_port = udp_port

diff --git a/misoclib/com/liteeth/test/arp_tb.py b/misoclib/com/liteeth/test/arp_tb.py
@@ -4,7 +4,7 @@
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 from misoclib.com.liteeth.core.arp import LiteEthARP
 
 from misoclib.com.liteeth.test.common import *

diff --git a/misoclib/com/liteeth/test/mac_core_tb.py b/misoclib/com/liteeth/test/mac_core_tb.py
@@ -4,7 +4,7 @@
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac.core import LiteEthMACCore
+from misoclib.com.liteeth.core.mac.core import LiteEthMACCore
 
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac

diff --git a/misoclib/com/liteeth/test/mac_wishbone_tb.py b/misoclib/com/liteeth/test/mac_wishbone_tb.py
@@ -4,7 +4,7 @@
 from migen.sim.generic import run_simulation
 
 from misoclib.com.liteeth.common import *
-from misoclib.com.liteeth.mac import LiteEthMAC
+from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 from misoclib.com.liteeth.test.common import *
 from misoclib.com.liteeth.test.model import phy, mac

diff --git a/misoclib/com/litepcie/example_designs/targets/dma.py b/misoclib/com/litepcie/example_designs/targets/dma.py
@@ -6,13 +6,14 @@
 
 from misoclib.soc import SoC
 from misoclib.tools.litescope.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeUART2Wishbone
+
+from misoclib.com.uart.frontend.wishbone import UARTWishboneBridge
 
 from misoclib.com.litepcie.phy.s7pciephy import S7PCIEPHY
 from misoclib.com.litepcie.core import Endpoint
 from misoclib.com.litepcie.core.irq.interrupt_controller import InterruptController
 from misoclib.com.litepcie.frontend.dma import DMA
-from misoclib.com.litepcie.frontend.bridge.wishbone import WishboneBridge
+from misoclib.com.litepcie.frontend.wishbone import LitePCIeWishboneBridge
 
 
 class _CRG(Module, AutoCSR):
@@ -61,7 +62,7 @@ def __init__(self, platform, with_uart_bridge=True):
         clk_freq = 125*1000000
         SoC.__init__(self, platform, clk_freq,
             cpu_type="none",
-            shadow_address=0x00000000,
+            shadow_base=0x00000000,
             with_csr=True, csr_data_width=32,
             with_uart=False,
             with_identifier=True,
@@ -74,15 +75,15 @@ def __init__(self, platform, with_uart_bridge=True):
         self.submodules.pcie_endpoint = Endpoint(self.pcie_phy, with_reordering=True)
 
         # PCIe Wishbone bridge
-        self.add_cpu_or_bridge(WishboneBridge(self.pcie_endpoint, lambda a: 1))
+        self.add_cpu_or_bridge(LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1))
         self.add_wb_master(self.cpu_or_bridge.wishbone)
 
         # PCIe DMA
         self.submodules.dma = DMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
         self.dma.source.connect(self.dma.sink)
 
         if with_uart_bridge:
-            self.submodules.uart_bridge = LiteScopeUART2Wishbone(platform.request("serial"), clk_freq, baudrate=115200)
+            self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
             self.add_wb_master(self.uart_bridge.wishbone)
 
         # IRQs

diff --git a/misoclib/com/litepcie/example_designs/test/make.py b/misoclib/com/litepcie/example_designs/test/make.py
@@ -21,15 +21,15 @@ def _get_args():
 if __name__ == "__main__":
     args = _get_args()
     if args.bridge == "uart":
-        from misoclib.tools.litescope.software.driver.uart import LiteScopeUART2WishboneDriver
+        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
         port = args.port if not args.port.isdigit() else int(args.port)
-        wb = LiteScopeUART2WishboneDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+        wb = UARTWishboneBridgeDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "etherbone":
-        from misoclib.tools.litescope.software.driver.etherbone import LiteScopeEtherboneDriver
-        wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
+        from misoclib.com.liteeth.software.wishbone import LiteETHWishboneDriver
+        wb = LiteETHWishboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
     elif args.bridge == "pcie":
-        from misoclib.tools.litescope.software.driver.pcie import LiteScopePCIeDriver
-        wb = LiteScopePCIeDriver(args.bar, args.bar_size, "./csr.csv", int(args.busword), debug=False)
+        from misoclib.com.litepcie.software.linux.wishbone import LitePCIeWishboneDriver
+        wb = LitePCIeWishboneDriver(args.bar, args.bar_size, "./csr.csv", int(args.busword), debug=False)
     else:
         ValueError("Invalid bridge {}".format(args.bridge))
 

diff --git a/.../com/litepcie/frontend/bridge/wishbone.py → misoclib/com/litepcie/frontend/wishbone.py b/.../com/litepcie/frontend/bridge/wishbone.py → misoclib/com/litepcie/frontend/wishbone.py
@@ -5,7 +5,7 @@
 from misoclib.com.litepcie.common import *
 
 
-class WishboneBridge(Module):
+class LitePCIeWishboneBridge(Module):
     def __init__(self, endpoint, address_decoder):
         self.wishbone = wishbone.Interface()
 

diff --git a/misoclib/cpu/peripherals/__init__.py → misoclib/com/litepcie/software/__init__.py b/misoclib/cpu/peripherals/__init__.py → misoclib/com/litepcie/software/__init__.py
diff --git a/...b/tools/litescope/software/driver/pcie.py → misoclib/com/litepcie/software/wishbone.py b/...b/tools/litescope/software/driver/pcie.py → misoclib/com/litepcie/software/wishbone.py
@@ -1,9 +1,11 @@
 import string
 import mmap
+import sys
+
 from misoclib.tools.litescope.software.driver.reg import *
 
 
-class LiteScopePCIeDriver:
+class LitePCIeWishboneDriverLinux:
     def __init__(self, bar, bar_size, addrmap=None, busword=8, debug=False):
         self.bar = bar
         self.bar_size = bar_size
@@ -54,3 +56,10 @@ def write(self, addr, data):
             self.mmap[addr + 4*i:addr + 4*(i+1)] = bytes(dat_bytes)
             if self.debug:
                 print("WR {:08X} @ {:08X}".format(dat, (addr + i)*4))
+
+
+def LitePCIeWishboneDriver(*args, **kwargs):
+    if sys.platform == "win32" or sys.platform == "cygwin":
+        raise NotImplementedError
+    else:
+        return LitePCIeWishboneDriverLinux(*args, **kwargs)
diff --git a/misoclib/com/liteusb/frontend/wishbone.py b/misoclib/com/liteusb/frontend/wishbone.py
@@ -1,14 +1,9 @@
 from migen.fhdl.std import *
 
 from misoclib.com.liteusb.common import *
-from misoclib.tools.litescope.bridge.wishbone import LiteScopeWishboneBridge
+from misoclib.tools.litescope.frontend.wishbone import LiteScopeWishboneBridge
 
 class LiteUSBWishboneBridge(LiteScopeWishboneBridge):
     def __init__(self, port, clk_freq):
         LiteScopeWishboneBridge.__init__(self, port, clk_freq)
-        self.comb += [
-            port.sink.sop.eq(1),
-            port.sink.eop.eq(1),
-            port.sink.length.eq(1),
-            port.sink.dst.eq(port.tag)
-        ]
+        self.comb += port.sink.dst.eq(port.tag)
diff --git a/misoclib/com/liteusb/software/ftdi/__init__.py b/misoclib/com/liteusb/software/ftdi/__init__.py
@@ -179,10 +179,15 @@ def __init__(self, tag):
             self.q = queue.Queue()
 
         def get_packet_size(self, buf):
-            return 10
+            payload_size = buf[5] << 24
+            payload_size |= buf[6] << 16
+            payload_size |= buf[7] << 8
+            payload_size |= buf[8] << 0
+            return 9 + payload_size
 
         def consume(self, buf):
-            self.q.put(buf[9])
+            for value in buf[9:]:
+                self.q.put(value)
 
     def __init__(self, tag):
         self.tag = tag
@@ -195,8 +200,18 @@ def do_read(self, timeout=None):
             return -1
         return resp
 
-    def do_write(self, value):
-        msg = [0x5A, 0xA5, 0x5A, 0xA5, self.tag, 0x00, 0x00, 0x00, 1, value&0xFF]
+    def do_write(self, data):
+        if isinstance(data, int):
+            data = [data]
+        msg = [0x5A, 0xA5, 0x5A, 0xA5]
+        msg.append(self.tag)
+        length = len(data)
+        msg.append((length >> 24) & 0xff)
+        msg.append((length >> 16) & 0xff)
+        msg.append((length >> 8) & 0xff)
+        msg.append((length >> 0) & 0xff)
+        for value in data:
+            msg.append(value&0xff)
         self.service.write(bytes(msg))
 
 
@@ -339,8 +354,8 @@ def uartflush(self, timeout=0.25):
     def uartread(self, timeout=None):
         return self.uart.do_read(timeout)
 
-    def uartwrite(self, value):
-        return self.uart.do_write(value)
+    def uartwrite(self, data):
+        return self.uart.do_write(data)
 
     def dmaread(self):
         return self.dma.do_read()

diff --git a/...ib/tools/litescope/software/driver/usb.py → misoclib/com/liteusb/software/wishbone.py b/...ib/tools/litescope/software/driver/usb.py → misoclib/com/liteusb/software/wishbone.py
@@ -1,11 +1,11 @@
 from misoclib.com.liteusb.software.ftdi import FTDIComDevice
 
-class LiteScopeUSB2WishboneFTDIDriver:
+class LiteUSBWishboneDriverFTDI:
     cmds = {
         "write": 0x01,
         "read":  0x02
     }
-    def __init__(self, interface, mode, tag, addrmap=None, debug=False):
+    def __init__(self, interface, mode, tag, addrmap=None, busword=8, debug=False):
         self.interface = interface
         self.mode = mode
         self.tag = tag
@@ -24,17 +24,18 @@ def open(self):
     def close(self):
         self.com.close()
 
-    # XXX regroup cmds in a single packet
     def read(self, addr, burst_length=1):
         datas = []
+        msg = []
         self.com.uartflush()
-        self.com.uartwrite(self.cmds["read"])
-        self.com.uartwrite(burst_length)
+        msg.append(self.cmds["read"])
+        msg.append(burst_length)
         word_addr = addr//4
-        self.com.uartwrite((word_addr >> 24) & 0xff)
-        self.com.uartwrite((word_addr >> 16) & 0xff)
-        self.com.uartwrite((word_addr >> 8) & 0xff)
-        self.com.uartwrite((word_addr >> 0) & 0xff)
+        msg.append((word_addr >> 24) & 0xff)
+        msg.append((word_addr >> 16) & 0xff)
+        msg.append((word_addr >> 8) & 0xff)
+        msg.append((word_addr >> 0) & 0xff)
+        self.com.uartwrite(msg)
         for i in range(burst_length):
             data = 0
             for k in range(4):
@@ -48,24 +49,32 @@ def read(self, addr, burst_length=1):
         else:
             return datas
 
-    # XXX regroup cmds in a single packet
     def write(self, addr, data):
         if isinstance(data, list):
             burst_length = len(data)
         else:
             burst_length = 1
             data = [data]
-        self.com.uartwrite(self.cmds["write"])
-        self.com.uartwrite(burst_length)
+        msg = []
+        msg.append(self.cmds["write"])
+        msg.append(burst_length)
         word_addr = addr//4
-        self.com.uartwrite((word_addr >> 24) & 0xff)
-        self.com.uartwrite((word_addr >> 16) & 0xff)
-        self.com.uartwrite((word_addr >> 8) & 0xff)
-        self.com.uartwrite((word_addr >> 0) & 0xff)
+        msg.append((word_addr >> 24) & 0xff)
+        msg.append((word_addr >> 16) & 0xff)
+        msg.append((word_addr >> 8) & 0xff)
+        msg.append((word_addr >> 0) & 0xff)
         for i in range(len(data)):
             dat = data[i]
             for j in range(4):
-                self.com.uartwrite((dat >> 24) & 0xff)
+                msg.append((dat >> 24) & 0xff)
                 dat = dat << 8
             if self.debug:
                 print("WR {:08X} @ {:08X}".format(data[i], addr + 4*i))
+        self.com.uartwrite(msg)
+
+
+def LiteUSBWishboneDriver(chip="ft2232h", *args, **kwargs):
+    drivers = {
+        "ft2232h": LiteUSBWishboneDriverFTDI
+    }
+    return drivers[chip](*args, **kwargs)
diff --git a/misoclib/tools/litescope/bridge/__init__.py → misoclib/com/uart/frontend/__init__.py b/misoclib/tools/litescope/bridge/__init__.py → misoclib/com/uart/frontend/__init__.py