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1 parent d8fdac6 commit cb65b1eCopy full SHA for cb65b1e
artiq/gateware/rtio/phy/ttl_simple.py
@@ -26,12 +26,11 @@ def __init__(self, pad):
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sensitivity = Signal(2)
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self.sync.rio_phy += If(self.rtlink.o.stb,
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- Case(self.rtlink.o.address, {
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- 0: ts.o.eq(self.rtlink.o.data[0]),
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- 1: ts.oe.eq(self.rtlink.o.data[0]),
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- 2: sensitivity.eq(self.rtlink.o.data)
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- }).makedefault()
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- )
+ If(self.rtlink.o.address == 0, ts.o.eq(self.rtlink.o.data[0])),
+ If(self.rtlink.o.address == 1, ts.oe.eq(self.rtlink.o.data[0])),
+ )
+ self.sync.rio += If(self.rtlink.o.stb & (self.rtlink.o.address == 2),
+ sensitivity.eq(self.rtlink.o.data))
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i = Signal()
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i_d = Signal()
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