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base repository: m-labs/artiq
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base: 136d44d9db79
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head repository: m-labs/artiq
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compare: 6e5b71a43e84
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  • 2 commits
  • 3 files changed
  • 1 contributor

Commits on Sep 3, 2015

  1. dds: increase DAC calibration time

    @sbourdeauducq
    sbourdeauducq committed Sep 3, 2015

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    8253739 View commit details

  2. coredevice/comm_tcp: disable socket timeout after connect 

    Reads may block indefinitely.
    @sbourdeauducq
    sbourdeauducq committed Sep 3, 2015
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    6e5b71a View commit details
Showing with 4 additions and 3 deletions.
  1. +1 −0 artiq/coredevice/comm_tcp.py
  2. +2 −2 soc/runtime/dds.c
  3. +1 −1 soc/runtime/ksupport.c
1 change: 1 addition & 0 deletions artiq/coredevice/comm_tcp.py
View file
Original file line number Diff line number Diff line change
@@ -33,6 +33,7 @@ def open(self):
if hasattr(self, "socket"):
return
self.socket = socket.create_connection((self.host, self.port), 5.0)
self.socket.settimeout(None)
set_keepalive(self.socket, 3, 2, 3)
logger.debug("connected to host %s on port %d", self.host, self.port)
self.write(b"ARTIQ coredev\n")
4 changes: 2 additions & 2 deletions soc/runtime/dds.c
View file
Original file line number Diff line number Diff line change
@@ -15,8 +15,8 @@

#elif defined DDS_AD9914
/* Assume 16-bit bus */
/* DAC calibration takes max. 135us as per datasheet. Take a good margin. */
#define DURATION_DAC_CAL (30000 << RTIO_FINE_TS_WIDTH)
/* DAC calibration takes max. 1ms as per datasheet */
#define DURATION_DAC_CAL (147000 << RTIO_FINE_TS_WIDTH)
/* not counting final FUD */
#define DURATION_INIT (10*DURATION_WRITE + DURATION_DAC_CAL)
#define DURATION_PROGRAM (5*DURATION_WRITE) /* not counting FUD */
2 changes: 1 addition & 1 deletion soc/runtime/ksupport.c
View file
Original file line number Diff line number Diff line change
@@ -79,7 +79,7 @@ long long int now_init(void)

if(now < 0) {
rtio_init();
now = rtio_get_counter() + (125000 << RTIO_FINE_TS_WIDTH);
now = rtio_get_counter() + (272000 << RTIO_FINE_TS_WIDTH);
}

return now;